四族異質結構中的量子傳輸特性

Abstract

由於量子電腦具備大規模平行計算的能力，因此預期具有超越古典電腦的計算能力。此外，由於矽基自旋量子位元具備在1 K 溫度以上工作的能力，可透過超大型積體電路製程進行生產、同時能與控制/讀取等週邊電路進行整合，因此矽基自旋量子位元被寄厚望以實現量子計算系統。為了減少與室溫控制/讀取設備相連時，由長導線所衍生如訊號延遲等問題，週邊電路應置於矽基量子位元周遭。然而由於電晶體的低溫特性，如閥值電壓、次鄰界擺幅等等，並無法藉由室溫特性外插而得，尚須更一步研究。此外，由於氧化物/半導體界面存在不可避免的缺陷態，因而造成自旋量子位元的不穩定性與保真度下降。為了減少此類不穩定性，自旋量子位元須被製作於矽/矽鍺異質結構基材，並藉由矽鍺間隔層將載子侷限於量子井內，以遠離氧化物/半導體界面；但由於量子井的能量束縛小，導致載子能藉由穿隧效應逃逸至表面，進而對量子位元產生額外雜訊。近期研究表明由於鍺基自旋量子位元具有強自旋軌域耦合作用，使其操作速度遠高於矽基自旋量子位元近三個數量級；此外，藉由摻雜錫原子於鍺量子井，則可再進一步提升自旋軌域耦合作用。然而當前仍尚未見任何鍺錫相關量子元件。 本論文將針對矽基氧化物半導體場效應電晶體與矽/矽鍺異質結構場效應電晶體的低溫特行進行研究，並分析表面穿隧效應之穩態與暫態特性。此外，亦於鍺/鍺矽與鍺錫/鍺異質結構上製作與分析量子點接觸元件，並於鍺/鍺矽異質結構上製作與分析雙量子點元件。 在溫度 4 K下，矽基氧化物半導體場效應電晶體與矽/矽鍺異質結構場效應電晶體的次臨界擺幅分別可達23與6 mV/decade。由於深埋於量子井的傳輸通道能減輕來自表面缺陷態的影響，矽/矽鍺異質結構元件的次臨界擺幅是當前已知的最低數值。此外，藉由穩態與暫態特性分析，探討穿隧效應對於矽/矽鍺異質結構元件的載子分布與傳輸影響。暫態特性藉由施加閘極電壓一段固定時間後，再量測汲極電流──發現隨著電壓施加時間增加，汲極電流將持續下降。該現象可由幸運電子模型解釋，主要是因量子井產生額外載子流失至表面通道，一旦電晶體的汲極電壓增加、工作溫度上升、抑或通道長度增長，量子井內的載子便能獲得足夠能量克服能障穿隧至異質結構表面。隨著愈多的載子洩漏至表面，表面便會形成第二個通道，導致異質結構內出現並聯傳輸。本研究亦探討化學機械研磨法對於矽/矽鍺異質結構的影響，經過化學機械研磨的矽/矽鍺異質結構場效應電晶體存在較大的量子井載子洩漏，進而造成汲極電流下降與電晶體的二次導通現象，此效應也藉由分離式電容電壓量測法與暫態特性佐證。化學機械研磨後的矽鍺阻隔層可能存在非均勻電場分佈，而導致量子井載子洩漏增加。 接著在鍺/鍺矽與鍺錫/鍺異質結構上製作量子點接觸元件，研究其線性與非線性傳輸模式，同時亦針對磁場效應與非對稱分裂閘極電壓效應進行分析。在鍺/鍺矽的量子點接觸元件中，並未在線性傳輸模式下觀測到分數量子電導；然而在鍺錫/鍺的量子點接觸元件中，卻觀測到 0.7 G_0、0.5 G_0 與 0.25 G_0 分數電導平台。 0.75 G_0 與 0.25 G_0 的分數電導平台可能因一維傳輸通道中的自旋相依傳輸所致；而0.5 G_0 的分數電導平台則可歸因於鍺錫量子井中強Rashba自旋軌域耦合所引起的自旋極化電流──由於自旋簡併態的破壞，使得電導分數化於 e2/h (0.5 G_0)。此外，藉由增加汲極電壓以在非線性傳輸模式下操作元件，將同時破壞載子的動量與自旋簡併態，此時將導致鍺/鍺矽與鍺錫/鍺異質結構量子點接觸元件上皆出現顯著的 0.25 G_0 分數電導平台。此外，由於勞侖茲變換的緣故，垂直磁場(B_z)與非對稱分裂閘極電壓在兩種量子點接觸元件中展現類似結果。由於自旋簡併態受到破壞，因此在鍺/鍺矽量子點接觸元件中觀測到分數化於 e2/h (0.5 G_0) 的電導平台，包含 1.5 G_0、1.0 G_0 與 0.5 G_0；另一方面，則在鍺錫/鍺量子點接觸元件中觀測到分數化於 0.7 G_0 與 0.35 G_0 的異常現象，而需要更進一步的研究。

Quantum computers are predicted to outperform classical computers due to their computational power by the parallelism nature. Since Si-based qubits could be operated above 1 K and to be integrated with peripheral control and readout circuits by state-of-the-art VLSI technology, they are considered a promising platform for the realization of full-scale quantum computers. The peripheral circuits are placed near the qubits to reduce issues originating from long wires with room temperature control/readout equipment, such as signal latency. However, cryogenic characteristics of transistors, such as the threshold voltage or subthreshold swing (SS), could not be extrapolated from the characteristics at room temperature and require further investigations. On the other hand, due to the unavoidable trapped states at the oxide/semiconductor interface, those unwanted charges make Si-based spin-qubits unstable and reduce the qubit fidelity. To minimize the instability, spin-qubits are fabricated on Si/SiGe heterostructures to separate carriers from the oxide/semiconductor interface by a SiGe spacer with a quantum well (QW). However, due to a shallow energy confinement of the QW, carriers could escape from the QW to the surface by surface tunneling, resulting in additional noise to the qubits. Recently, Ge-based spin-qubits were demonstrated to have faster gate operation times than Si-based spin-qubits by a factor of ~ 103 due to strong spin-orbit coupling (SOC). Meanwhile, by incorporating Sn atoms into the Ge QW, SOC was found to be enhanced further. However, there is no report of quantum devices on any GeSn QW yet. In this work, cryogenic characteristics of Si MOSFETs and Si/SiGe heterostructure FETs are investigated, followed by careful studies of surface tunneling effects in Si/SiGe heterostructures through steady-state and transient characteristics. The quantum point contact (QPC) devices on a Ge/GeSi and a GeSn/Ge heterostructure are also fabricated and characterized. Finally, double quantum dots (QDs) on a Ge/GeSi heterostructure are fabricated and analyzed. SS of a Si MOSFET and a Si/SiGe heterostructure FETs are 23 and 6 mV/decade at 4 K, respectively. The SS of the Si/SiGe device is the lowest reported so far and can be attributed to the recessed transport channel to the buried Si QW in the Si/SiGe heterojunction with a reduced impact from the trapped states at the surface. The tunneling effect on the carrier distribution and transport properties of the Si/SiGe devices were investigated by steady-state and transient characteristics. For the transient characterization, the drain current is measured after biasing the gate for a hold time. With a longer hold time, the drain current was reduced, which is explained by a lucky electron model for the extra carrier loss from the Si QW. Once the carriers in the QW acquire sufficient energy to surmount the energy barrier by increasing the drain bias, temperature, or channel length, more carriers tunnel to the surface, leading to a reduced carrier density in the QW, followed by the onset of the surface channel and the parallel conduction of the heterostructures. The effects of chemical mechanical polishing (CMP) on the characteristics of Si/SiGe heterostructure FETs are also investigated. The Si/SiGe heterostructure FETs with CMP show further carrier loss from the QW, leading to a rapid reduction of the drain current, followed by the second turn-on of the FETs. The increasing carrier loss was supported by transient results and split-CV characteristics, which might be attributed to a non-uniformly distributed electric field across the SiGe spacer after CMP. QPC devices are fabricated on a Ge/GeSi and a GeSn/Ge heterostructure and characterized in a linear- or a nonlinear-transport regime. The effects of the magnetic field or asymmetric bias on split gates are also investigated. No fractional conductance is observed for the Ge/GeSi QPC device without a drain bias (i.e., in a linear-transport regime), while the fractional plateaus of 0.7 G_0, 0.5 G_0 and 0.25 G_0 are observed for the GeSn/Ge QPC device. 0.7 G_0 and 0.25 G_0 are attributed to spin-dependent transmissions in the 1D channel, and 0.5 G_0 is attributed to the spin-polarized current by strong Rashba SOC in the GeSn QW, which leads to a lift of spin degeneracy with the conductance quantized in e2/h (0.5 G_0). By further increasing the drain bias to operate the QPC devices in a nonlinear-transport regime, both Ge/GeSi and GeSn/Ge QPC devices show a prominent plateau of 0.25 G_0 due to the lift of momentum and spin degeneracy. Furthermore, the out-of-plane magnetic field (B_z) and the asymmetric bias on the split gates show similar results on both QPC devices due to the Lorentz transformation. The quantized conductance of e2/h (0.5 G_0) is observed for the Ge/GeSi QPC device due to the lift of spin degeneracy, leading to the presence of 1.5 G_0, 1.0 G_0 and 0.5 G_0. On the other hand, anomalies of 0.7 G_0 and 0.35 G_0 are observed on GeSn QPC, which requires further investigations.