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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/96194完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李泰成 | zh_TW |
| dc.contributor.advisor | Tai-Cheng Lee | en |
| dc.contributor.author | 陳品丞 | zh_TW |
| dc.contributor.author | Pin-Cheng Chen | en |
| dc.date.accessioned | 2024-11-28T16:07:36Z | - |
| dc.date.available | 2025-11-01 | - |
| dc.date.copyright | 2024-11-28 | - |
| dc.date.issued | 2024 | - |
| dc.date.submitted | 2024-09-13 | - |
| dc.identifier.citation | [1] C. Nguyen and J. Park, Stepped-Frequency Radar Sensors: Theory, Analysis and Design. Springer, first ed., 2016.
[2] B. Razavi, Design of CMOS Phase-Locked Loops. Cambridge University Press, first ed., 2020. [3] B. Razavi, RF Microelectronics. Prentice Hall, first ed., 1998. [4] W.-H. Chiu, Y.-H. Huang, and T.-H. Lin, “A Dynamic Phase Error Compensation Technique for Fast-Locking Phase-Locked Loops,” IEEE Journal of Solid-State Cir-cuits, vol. 45, pp. 1137–1149, June 2010. [5] W.-H. Chiu, T.-S. Chan, and T.-H. Lin, “A 5.5-GHz 16-mW fast-locking frequency synthesizer in 0.18-μm CMOS,” in 2007 IEEE Asian Solid-State Circuits Confer-ence, pp. 456–459, Nov 2007. [6] J.-R. Chang and S.-I. Liu, “A 2–3 GHz Fast-Locking PLL Using Phase Error Com-pensator,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, pp. 2026–2030, April 2022. [7] R.-J. Yang and S.-I. Liu, “A 40–550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm,” IEEE Journal of Solid-State Circuits, vol. 42, pp. 361–373, Feb 2007. [8] S. Levantino, C. Samori, A. Bonfanti, S. Gierkink, A. Lacaita, and V. Boccuzzi, “Frequency dependence on bias current in 5 GHz CMOS VCOs: impact on tuning range and flicker noise upconversion,” IEEE Journal of Solid-State Circuits, vol. 37, pp. 1003–1011, Aug 2002. [9] A. Hajimiri and T. Lee, “Design issues in CMOS differential LC oscillators,” IEEE Journal of Solid-State Circuits, vol. 34, pp. 717–724, May 1999. [10] S. S. Broussev, T. A. Lehtonen, and N. T. Tchamov, “A Wideband Low Phase-Noise LC-VCO With Programmable KVCO,” IEEE Microwave and Wireless Components Letters, vol. 17, pp. 274–276, April 2007. [11] D. J. Tony Carusone and K. Martin, Analog Integrated Circuit Design. Wiley, sec-ond ed., 2012. [12] I.-T. Lee, Y.-T. Tsai, and S.-I. Liu, “A fast-locking phase-locked loop using CP con-trol and gated VCO,” in Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, pp. 1–4, April 2012. [13] A. Hu, D. Liu, K. Zhang, L. Liu, and X. Zou, “A 0.045- to 2.5-GHz Frequency Synthesizer With TDC-Based AFC and Phase Switching Multi-Modulus Divider,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, pp. 4470–4483, Dec 2020. [14] F. ur Rahman, G. Taylor, and V. Sathe, “A 1–2 GHz Computational-Locking AD-PLL With Sub-20-Cycle Locktime Across PVT Variation,” IEEE Journal of Solid-State Circuits, vol. 54, pp. 2487–2500, Sep 2019. [15] Z. Yang, Y. Chen, S. Yang, P.-I. Mak, and R. P. Martins, “A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector,” IEEE Access, vol. 8, pp. 2222–2232, Jan 2020. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/96194 | - |
| dc.description.abstract | 本論文提出了一種具有聯合相位與頻率補償技術的快速鎖定之鎖相迴路。在最大相位誤差偵測器的幫助下，頻率獲取過程完成後會立即補償累積的相位誤差與電壓差，以加速鎖相迴路的鎖定時間。
此鎖相迴路利用28奈米技術製造並以供應電壓0.9伏進行量測，在1.012百億赫茲的輸出頻率下，該鎖相迴路功耗為2.76毫瓦。而均方根抖動由一萬赫茲積分至一億赫茲為491飛秒。整體的穩定時間在穩定精準度為0.02百分率下提升了78百分率。 | zh_TW |
| dc.description.abstract | In this thesis, we propose a fast-locking phase-locked loop (PLL) with joint phase and frequency compensation technique. With the aid of a maximum phase error detector (MPED), the accumulated phase error is compensated immediately after completing the frequency acquisition process, thereby improving the settling time of the PLL.
A prototype chip operating at a supply voltage of 0.9 V was fabricated using a 28-nm CMOS process. The output frequency of the PLL is 10.12 GHz, with a power consumption of 2.76 mW. The integral root-mean-square jitter over a range of 10 kHz to 100 MHz is 491 fs. The total settling time is improved by 78% under a settling accuracy of 0.02%. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2024-11-28T16:07:36Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2024-11-28T16:07:36Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | Contents
誌謝 ii 摘要 iii Abstract iv Contents v List of Figures viii List of Tables xi 1 Introduction 1 1.1 Motivation and Research Goal . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Basic Concepts 4 2.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1.1 Linear Model Analysis for CPPLL . . . . . . . . . . . . . . . . . 5 2.1.2 Settling Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Dynamic Behavior of the PLL . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Prior Arts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4 Review of First Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 System Architecture and Implementation 15 3.1 Operation principle of the proposed technique . . . . . . . . . . . . . . . 15 3.2 Proposed Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3 Maximum Phase Error Determination . . . . . . . . . . . . . . . . . . . 18 3.4 Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4.1 Maximum Phase Error Detector (MPED) . . . . . . . . . . . . . 20 3.4.2 Phase Compensator . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.4.3 Voltage Compensator . . . . . . . . . . . . . . . . . . . . . . . . 28 3.4.4 Phase Frequency Detector . . . . . . . . . . . . . . . . . . . . . 33 3.4.5 Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.4.6 Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.4.7 Voltage-Controlled Oscillator . . . . . . . . . . . . . . . . . . . 38 3.4.8 Non-ideal effects of the compensation blocks . . . . . . . . . . . 46 3.5 Simulation results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.5.1 Systematic Verification of the Proposed Architecture . . . . . . . 48 3.5.2 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . 50 3.5.3 Phase Noise and Jitter . . . . . . . . . . . . . . . . . . . . . . . 51 4 Measurement Results 52 4.1 Chip Die-photo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4.2 Printed Circuit Board Design . . . . . . . . . . . . . . . . . . . . . . . . 53 4.3 Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4.4 Measurement Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.4.1 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . 55 4.4.2 Phase Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.4.3 Settling Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.5 Comparison and Summary . . . . . . . . . . . . . . . . . . . . . . . . . 58 5 Conclusion 59 5.1 Thesis Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Bibliography 60 | - |
| dc.language.iso | en | - |
| dc.subject | 頻率補償 | zh_TW |
| dc.subject | 最大相位誤差偵測 | zh_TW |
| dc.subject | 鎖相迴路 | zh_TW |
| dc.subject | 相位補償 | zh_TW |
| dc.subject | 快速鎖定 | zh_TW |
| dc.subject | frequency compensation | en |
| dc.subject | Phase-locked loop | en |
| dc.subject | fast-locking | en |
| dc.subject | maximum phase error detection | en |
| dc.subject | phase error compensation | en |
| dc.title | 具有聯合相位與頻率補償技術之快速鎖定鎖相迴路 | zh_TW |
| dc.title | A Fast-Locking Phase-Locked Loop with Joint Phase and Frequency Compensation Technique | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 113-1 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 劉深淵;林宗賢;陳筱青 | zh_TW |
| dc.contributor.oralexamcommittee | Shen-Iuan Liu;Tsung-Hsien Lin;Hsiao-Chin Chen | en |
| dc.subject.keyword | 鎖相迴路,快速鎖定,最大相位誤差偵測,相位補償,頻率補償, | zh_TW |
| dc.subject.keyword | Phase-locked loop,fast-locking,maximum phase error detection,phase error compensation,frequency compensation, | en |
| dc.relation.page | 61 | - |
| dc.identifier.doi | 10.6342/NTU202404374 | - |
| dc.rights.note | 未授權 | - |
| dc.date.accepted | 2024-09-13 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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