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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 楊佳玲 | zh_TW |
| dc.contributor.advisor | Chia-Lin Yang | en |
| dc.contributor.author | 陳炫均 | zh_TW |
| dc.contributor.author | Xuan-Jun Chen | en |
| dc.date.accessioned | 2024-11-20T16:09:04Z | - |
| dc.date.available | 2024-11-21 | - |
| dc.date.copyright | 2024-11-20 | - |
| dc.date.issued | 2024 | - |
| dc.date.submitted | 2024-11-07 | - |
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/96186 | - |
| dc.description.abstract | 記憶體內運算架構已證明其有效解決記憶體牆瓶頸的能力，神經網路結構搜索致力於自動化機器學習模型的設計。然而，若欲整合記憶體內運算架構至神經網路結構搜索中，將出現重大的挑戰。在記憶體內運算加速器上部署神經網路，會引入與硬體相關的因素，導致大量額外的模擬負擔。本論文透過結合量化和裝置感知的準確率預測器，介紹了一種超高效的記憶體內運算和神經網路的架構搜索框架。此外，我們邁出了第一步，在定量分析資訊如何於記憶體內運算的神經網路加速器中傳播，以及額外的記憶體內運算因素如何影響該訊息傳播。另一方面，本論文介紹了第一個利用記憶體內運算的最佳化機會，來解決記憶體效率低下問題的點雲深度學習分析加速器，而後我們也基於所提出的記憶體內運算架構，利用神經網路結構搜索的技術來探索最佳的點雲模型。 | zh_TW |
| dc.description.abstract | Computing-in-memory (CIM) architecture has demonstrated its ability to address the memory wall bottleneck effectively. Neural architecture search (NAS) endeavors to design machine learning models automatically. However, integrating CIM into NAS presents a significant challenge. Deploying neural networks on CIM accelerators introduces hardware-related factors, resulting in substantial additional simulation overhead. This dissertation introduces an ultra-efficient CIM-NAS framework by incorporating a quantization and device aware accuracy predictor. In addition, we take the first step in quantitative analysis of how information propagates in CIM neural accelerators and how additional CIM factors influence that information propagation. On the other hand, this dissertation introduces the first deep point cloud (PC) analytics, an emerging machine learning application, accelerator that leverages CIM optimization opportunities to address memory inefficiency. We also explore optimal PC models based on the proposed CIM architecture using NAS techniques. | en |
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| dc.description.provenance | Made available in DSpace on 2024-11-20T16:09:04Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | Verification Letter from the Oral Examination Committee . . . i
Acknowledgements . . . iii 摘要 . . . v Abstract . . . vii Contents . . . ix List of Figures . . . xiii List of Tables . . . xvii Denotation . . . xix Chapter 1 Introduction . . . 1 Chapter 2 Background . . . 5 2.1 NAS . . . 5 2.2 CIM DNN Accelerator . . . 6 2.3 LDI . . . 7 2.4 Deep PC Analytics . . . 8 Chapter 3 Joint Search for DNN and CIM Architecture . . . 11 3.1 Challenges for NAS on CIM Architecture . . . 12 3.2 Opportunity of Employing Predictor-based NAS . . . 14 3.3 CIMNet: Co-Search Framework . . . 16 3.3.1 Overview . . . 17 3.3.2 Search Space Reduction . . . 18 3.3.2.1 Cell Resolution Aware Quantization . . . 18 3.3.2.2 Convolution Layer Choice: Standard vs. Depthwise . . . 19 3.3.2.3 Layer-Customized Weight Mapping Policy . . . 21 3.3.3 Method . . . 22 3.3.3.1 Search Space . . . 22 3.3.3.2 Quantization and Device Aware Accuracy Predictor . . . 23 3.3.3.3 Latency/Energy Estimation . . . 25 3.3.3.4 Search Engine . . . 26 3.4 Experiments . . . 27 3.4.1 Experimental Setup . . . 27 3.4.2 Searched Results . . . 28 3.4.3 Analysis . . . 28 3.4.3.1 Accuracy . . . 28 3.4.3.2 Latency . . . 29 3.4.3.3 Energy Consumption . . . 30 3.4.4 Comparison against Other CIM-NAS Works . . . 31 3.4.4.1 Quality . . . 31 3.4.4.2 Efficiency . . . 32 Chapter 4 Unified Agile Accuracy Assessment in CIM Neural Accelerators . . . 33 4.1 Method . . . 37 4.1.1 Ideal Layerwise Jacobian . . . 38 4.1.2 Layerwise Jacobian for Error . . . 39 4.1.3 Factors in Error . . . 42 4.1.3.1 Weight Precision . . . 43 4.1.3.2 Analog-to-Digital Converter . . . 44 4.1.3.3 Cell Variation . . . 44 4.1.4 Overall Layerwise Jacobian . . . 46 4.2 Experiments . . . 49 4.2.1 Experimental Setup . . . 49 4.2.2 Results . . . 49 4.2.3 Discussion . . . 50 Chapter 5 A CIM Architecture for Accelerating Deep PC Analytics . . . 51 5.1 Computation Optimization of PointCIM . . . 55 5.1.1 Challenges for In-Memory PC Network Inference . . . 55 5.1.2 Base+Offset Mapping . . . 57 5.1.3 Early-Stopping Optimization for Bit-Serial Computation . . . 59 5.2 PointCIM Hardware Architecture . . . 62 5.2.1 Signed Arithmetic . . . 63 5.2.2 Margin Calculation . . . 64 5.2.3 Point Feature Read . . . 65 5.2.4 Morton Code-Based Crossbar Interleaving . . . 65 5.2.5 Pipelined Execution . . . 66 5.2.6 Max/Top-K Logic . . . 67 5.3 Evaluation . . . 68 5.3.1 Methodology . . . 68 5.3.1.1 Workloads . . . 68 5.3.1.2 Hardware Configuration . . . 68 5.3.1.3 Accelerator Synthesis and Simulation . . . 69 5.3.1.4 Comparison Baselines . . . 70 5.3.2 Overall Results . . . 71 5.3.2.1 Accuracy . . . 71 5.3.2.2 Speedup . . . 71 5.3.2.3 Energy Consumption . . . 72 5.3.2.4 Area . . . 72 5.3.3 Optimization Effects . . . 73 5.3.3.1 Early Stopping for Bit-Serial Computation . . . 73 5.3.3.2 Morton Code-Based Crossbar Interleaving . . . 73 5.3.4 Sensitivity Studies . . . 74 5.3.4.1 DAC Resolution . . . 74 5.3.4.2 Number of CUs . . . 75 5.3.5 Other Results . . . 76 5.3.5.1 Comparison with E2-MCAM . . . 76 5.3.5.2 End-to-End System Efficiency . . . 76 5.3.5.3 PC Model Exploration . . . 77 Chapter 6 Conclusion . . . 93 References . . . 95 | - |
| dc.language.iso | en | - |
| dc.subject | 點雲深度學習分析 | zh_TW |
| dc.subject | 量化 | zh_TW |
| dc.subject | 神經網路結構搜索 | zh_TW |
| dc.subject | 記憶體內運算加速器 | zh_TW |
| dc.subject | Deep Point Cloud Analytics | en |
| dc.subject | Computing-in-Memory Accelerator | en |
| dc.subject | Neural Architecture Search | en |
| dc.subject | Quantization | en |
| dc.title | 神經網路和記憶體內運算架構共同設計 | zh_TW |
| dc.title | Neural Network and Computing-in-Memory Architecture Co-Design | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 113-1 | - |
| dc.description.degree | 博士 | - |
| dc.contributor.oralexamcommittee | 郭大維;胡璧合;張原豪;鄭湘筠 | zh_TW |
| dc.contributor.oralexamcommittee | Tei-Wei Kuo;Pi-Ho Hu;Yuan-Hao Chang;Hsiang-Yun Cheng | en |
| dc.subject.keyword | 記憶體內運算加速器,神經網路結構搜索,量化,點雲深度學習分析, | zh_TW |
| dc.subject.keyword | Computing-in-Memory Accelerator,Neural Architecture Search,Quantization,Deep Point Cloud Analytics, | en |
| dc.relation.page | 108 | - |
| dc.identifier.doi | 10.6342/NTU202404552 | - |
| dc.rights.note | 未授權 | - |
| dc.date.accepted | 2024-11-07 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 資訊工程學系 | - |
| 顯示於系所單位： | 資訊工程學系 | |
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