Please use this identifier to cite or link to this item:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/95984Full metadata record
| ???org.dspace.app.webui.jsptag.ItemTag.dcfield??? | Value | Language |
|---|---|---|
| dc.contributor.advisor | 李致毅 | zh_TW |
| dc.contributor.advisor | Jri Lee | en |
| dc.contributor.author | 林裕叡 | zh_TW |
| dc.contributor.author | Yu-Ruei Lin | en |
| dc.date.accessioned | 2024-09-25T16:28:11Z | - |
| dc.date.available | 2024-09-26 | - |
| dc.date.copyright | 2024-09-25 | - |
| dc.date.issued | 2024 | - |
| dc.date.submitted | 2024-09-16 | - |
| dc.identifier.citation | H. Arora, N. Klemmer, J. Morizio, and P. Wolf. Enhanced phase noise modeling offractional-n frequency synthesizers. IEEE Transactions on Circuits and Systems I:Regular Papers, 52(2):379–395, 2005.
N. Da Dalt and A. Sheikholeslami. Understanding Jitter and Phase Noise: A Circuits and Systems Perspective. Cambidge: Cambridge university press, 2018. A. Hajimiri, S. Limotyrakis, and T. Lee. Jitter and phase noise in ring oscillators. IEEE Journal of Solid-State Circuits, 34(6):790–804, 1999. P. Larsson. An offset-cancelled cmos clock-recovery/ demux with a half-rate linear phase detector for 2.5 gb/ s optical communication. In 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177), pages 74–75, 2001. B. Razavi. The role of plls in future wireline transmitters. IEEE Transactions on Circuits and Systems I: Regular Papers, 56(8):1786–1793, 2009. T. Riley, M. Copeland, and T. Kwasniewski. Delta-sigma modulation in fractional-n frequency synthesis. IEEE Journal of Solid-State Circuits, 28(5):553–559, 1993. K. Shu and E. Sabchez-Sinencio. Loop Filter with Capacitance Multiplier, pages 127–150. Springer US, Boston, MA, 2005. B. Çatlı, A. Nazemi, T. Ali, S. Fallahi, Y. Liu, J. Kim, M. Abdul-Latif, M. R. Ahmadi, H. Maarefi, A. Momtaz, and N. Kocaman. A sub-200 fs rms jitter capacitor multiplier loop filter-based pll in 28 nm cmos for high-speed serial communication applications. In Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, pages 1–4, 2013. 吳昇翰. 應用於 usb3 之資料時脈回復電路 / 吳昇翰 [撰] = a clock and datarecovery circuit applied for usb3 / sheng-han wu, 2022. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/95984 | - |
| dc.description.abstract | 此篇論文以 ∆Σ 非整數型鎖相迴路為設計基礎，採用 T55 技術製造，並通過頻譜分析儀和商用 USB3.2 CTS 測試進行了測量。通過嵌入式 FIR 噪音過濾技術，打破了震盪器噪音和 ∆Σ 量化噪音之間的折衷。在相位噪音輪廓中，中頻段頻率大約有 10dB 的改善。提出了一種數位控制延遲器偏置生成和校準技術，以應對電荷泵線性問題。數位控制延遲器校準技術減少了 20% 的相位噪音。這種技術可以消除低頻率因電流泵線性度不佳造成的相位噪聲。採用取樣迴路濾波器技術以避免大的參考擾動。達到了-62.48dBc 的參考擾動的結果。最後，實現了 4500ppm的展頻功能以符合 USB3.2 CTS 測試。此設計在所有測項上都通過了 USB3.2 的商用規格。 | zh_TW |
| dc.description.abstract | A Delta-Sigma fractional-N PLL design isdemonstrated, fabrcated in T55 technol ogy and measured by spectrum analyzer and commercial USB3.2 CTS test. A trade-off between VCO noise and Delta-Sigma quantization noise is broken by embedded FIR noisefiltering technique. Around 10dB improves in mid band frequency could be found in phasenoise profile. A DCDL offset generation and calibration technique is proposed to deal with the charge pump linearity issue. 20% phase noise is reduced by DCDL calibration technique. The aliased low frequency is cancelled by such technique. Sampling Loop filter technique is used to avoid large reference spur. A -62.48dBc reference spur result is available. Finally, 4500ppm Spread spectrum function is implemented for the USB3.2 CTS test. All the specification are pass in such test with our design. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2024-09-25T16:28:11Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2024-09-25T16:28:11Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 口試委員審定書 i
誌謝 ii 中文摘要 iii 英文摘要 iv 目次 v 圖次 viii 表次 xi 第一章 Introduction 1 1.1 Introduction 1 1.2 Jitter Introduction 1 1.3 Mathematical Jitter Model 3 1.4 Phase noise and Jitter 4 1.5 Spectral tone and Jitter 6 第二章 Jitter analysis 8 2.1 Deterministic Jitter analysis 8 2.2 Phase noise calculation 10 2.2.1 Type-II system 10 2.2.2 VCO phase noise transfer function 11 2.2.3 Charge pump phase noise transfer function 11 2.2.4 Loop filter phase noise transfer function 12 2.2.5 Power noise transfer function 13 2.3 Delta-Sigma Quantization Noise 13 2.3.1 Stability and Model extension 15 第三章 Building Blocks Design 19 3.1 Phase Frequency Detector Design 19 3.1.1 Dead Zone 20 3.1.2 Blind Zone 20 3.1.3 Phase noise 21 3.1.4 Proposed Design 22 3.2 Charge Pump Design 23 3.2.1 Phase Noise of Charge Pump 23 3.2.2 Nonlinearity source in Charge Pump 25 3.2.3 Proposed Design 27 3.3 Loop Filter Design 28 3.3.1 Cap. multiplication technique 29 3.3.1.1 Passive Loop Filter 29 3.3.1.2 Dual path Loop Filter 31 3.3.1.3 Larrson Loop Filter 32 3.3.2 Phase Noise of the Larrson Cap. Multiplication 33 3.3.3 Sampling Loop filter 34 3.4 Ring Oscillator Design 35 3.4.1 Phase Noise of the Ring Oscillator 35 3.4.2 Proposed Design 37 3.5 Frequency Divider Design 38 3.5.1 Sub-Sampling Effect 39 第四章 Loop Implementation 42 4.1 Automatic VCO Band Selection 43 4.2 DCDL Calibration 44 4.3 MASH 1-1-1 47 4.4 FCW 49 4.5 FIR Implementation 50 4.6 Asynchronous FIFO 54 第五章 Measurement Result 55 5.1 Measurement setup 55 5.2 Measurement result 57 5.2.1 Direct phase noise and SSC spectrum measurement 57 5.2.2 USB3.2 standard CTS(Compatibility Test Suite) testing 59 參考文獻 62 | - |
| dc.language.iso | en | - |
| dc.title | 一個具有展頻功能和有限衝激響應嵌入式雜訊過濾技術的 2.5GHz ∆Σ 非整數型鎖相迴路 | zh_TW |
| dc.title | A 2.5GHz Delta-Sigma Fractional-N PLL With SSC Function and FIR Embedded Noise Filtering Technique | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 113-1 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 謝秉璇;丁建均 | zh_TW |
| dc.contributor.oralexamcommittee | Ping-Hsuan Hsieh;Jian-Jiun Ding | en |
| dc.subject.keyword | 鎖相迴路,非整數型鎖相迴路,展頻技術,電荷泵線性度,噪聲濾除技術, | zh_TW |
| dc.subject.keyword | PLL,Fractional-N PLL,Spread spectrum clocking,Noise filtering technique, | en |
| dc.relation.page | 63 | - |
| dc.identifier.doi | 10.6342/NTU202403254 | - |
| dc.rights.note | 未授權 | - |
| dc.date.accepted | 2024-09-16 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| Appears in Collections: | 電子工程學研究所 | |
Files in This Item:
| File | Size | Format | |
|---|---|---|---|
| ntu-113-1.pdf Restricted Access | 6.68 MB | Adobe PDF |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.