具有相位誤差校正機制之正交相位壓控振盪器的實現與應用

Abstract

量子運算為關鍵的研究領域，其利用量子位元的疊加性和糾纏性能夠指數級地增加計算速度，從而有望在人工智慧應用中帶來革命性的進展。特定頻率的射頻訊號對於控制和讀取量子晶片中的量子位元至關重要。本研究針對超導量子位元所需的 4-8 GHz 頻率範圍提出正交相位壓控振盪器的設計。有鑑於廣泛應用於通訊收發器中的直接轉換架構，該架構利用正交相位本地振盪器直接將射頻訊號轉換至基頻，從而有效緩解鏡像問題，這是一項關鍵的電路技術。在文獻回顧中，先前的研究著重於低溫壓控振盪器的雜訊降低，但它們尚未能覆蓋 4-8 GHz 的調諧範圍。因此，本論文目標是設計一個能夠在 4 K 絕對溫度下維持 4-8 GHz 頻寬內保持精準正交相位精度的正交訊號產成器。 為了驗證提出的背閘控制技術可實現有效的相位調整，使用 0.18 μm CMOS 製程設計 16 GHz 正交壓控振盪器。量測到的頻率調整範圍是 15.66 到 16.16 GHz(3.14%)，在 16.15 GHz 載波頻率 1 MHz 偏移處的相位雜訊為 -105.55 dBc/Hz。在15.9 GHz 的振盪頻率下，測得的相位誤差為 3.32°，通過手動調整背閘電壓可將相位誤差降到幾乎為零。該相位誤差調整機制能夠調整大約 10° 的相位範圍，同時保持振福誤差在可接受的範圍內。 具有相位誤差自動校正機制適用於低溫 CMOS 應用的 4-8 GHz 正交相位壓控振盪器接著被提出，利用可切換電感的雙模 LC 共振腔和數位開關電容陣列以及連續調諧變容器實現寬頻調整範圍，此外，利用正交相位偵測器和運算放大器形成負回授來實現自動相位誤差校正機制。該電路使用 TSMC 90 nm CMOS 製程製造，在絕對溫度 4K 下測量到的頻率調整範圍為 3.48 到 7.68 GHz (75.3%)，在 1 MHz 偏移處的相位雜訊範圍為 -102.22 到 -114.41 dBc/Hz，在輸出頻率是 6.04 GHz 的狀態下，相位誤差自動校正機制將相位誤差從 4.56° 校正到 0.72°，每個振盪器消耗21.6 mW 的功率。

Quantum computing has emerged as a pivotal research area, leveraging the superposition and entanglement properties of qubits to exponentially enhance computational speed, thereby promising revolutionary advancements in AI applications. Specific frequency RF signals are crucial for controlling and reading qubits in quantum chips. This paper presents the design of a quadrature voltage-controlled oscillator (QVCO) targeting the 4-8 GHz range required for superconducting transmon qubits. Direct conversion architecture, widely utilized in communication transceivers, employs quadrature-phase local oscillators (LO) to directly convert RF to baseband, effectively mitigating image issues, which is a key circuit technology. The literature review indicates that while prior studies have focused on noise reduction in low-temperature VCOs, they fall short of covering the 4-8 GHz tuning range. Thus, our objective is to develop a quadrature generator capable of maintaining precise quadrature phase accuracy over a 4-8 GHz bandwidth at an absolute temperature of 4K. To validate the proposed back-gate control technique for effective phase adjustment, we designed a 16 GHz QVCO using TSMC 0.18-μm CMOS process. This QVCO, incorporating a self-switched biasing technique to enhance phase noise performance, demonstrates a tuning range from 15.66 to 16.16 GHz (3.14%) and a phase noise of -105.55 dBc/Hz at a 1 MHz offset from the 16.15 GHz carrier. At a 15.9 GHz oscillation frequency, the measured phase error is 3.32°, which can be reduced to nearly zero through manual adjustment of the body voltage. The phase adjustment mechanism allows for tuning the phase error over a range of approximately 10°, while keeping the amplitude error within acceptable limits. The paper further introduces a 4-8 GHz QVCO with an automatic phase error correction mechanism for cryo-CMOS applications. The circuit architecture leverages wide tuning range techniques and an automatic correction mechanism to achieve both wide bandwidth and precise phase performance. The wide tuning range is achieved using a switchable-inductor-based dual-mode LC-tank, combined with a digital switching capacitor bank and continuous tuning varactor. The automatic phase error correction mechanism utilizes a quadrature phase detector and an operational amplifier to form negative feedback, achieving automatic phase error correction. Implemented using TSMC 90 nm CMOS process, measurements at 4K reveal a frequency range from 3.48 to 7.68 GHz (75.3%), with 1 MHz offset phase noise ranging from -102.22 to -114.41 dBc/Hz. The automatic phase error correction mechanism reduces phase error from 4.56° to 0.72°, with each VCO consuming 21.6 mW of power.