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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/9519
標題: | 高頻CMOS鎖相迴路之設計與實現 Design and Implementation of High-frequency CMOS Phase-locked Loops |
作者: | Sin-Jhih Li 黎信志 |
指導教授: | 呂良鴻 |
關鍵字: | 高頻鎖相迴路,頻率偵測器,多相位控制, Phase-locked loop,PD,FD,multi-phased control, |
出版年 : | 2008 |
學位: | 碩士 |
摘要: | 本篇論文主題主要在介紹高頻鎖相迴路的設計與實作。論文中討論了數個方法以改善在高頻鎖相迴路中時脈擾動的情形。論文共分為六個章節,首先第一章對此篇論文作概略性的介紹,第二章則回顧鎖相迴路的背景知識。
第三章提出了一個使用多重相位控制的鎖相迴路架構。藉由此架構可有效抑制壓控震盪器控制電壓上來自參考時脈的週期性擾動,進而減少時脈鎖定時的擾動現象。此迴路架構使用了0.18-μm標準互補式金氧半導體製程加以實現,同時量測結果也會於本章呈現。 第四章將實現一個雙迴路的鎖相迴路架構。此架構可等效上減少迴路濾波器所需要的電容面積,故有助於單晶積體電路的整合。由於來自晶片外的元件雜訊減少了,時脈鎖定時的雜訊擾動現象也能因此有所改善。此鎖相迴路設計使用了0.18-μm標準互補式金氧半導體製程實作並且加以量測。 第五章將討論一個30-GHz的鎖相迴路設計。此設計採用了改良式的Colpitts壓控震盪器以減少壓控震盪本身所產生雜訊並使用了regenerative除頻器來增加如此高速下時脈信號的除頻範圍。此章將詳述此30-GHz鎖相迴路之設計流程與模擬結果。 This thesis illustrates the implementation of the high frequency phase-locked loops (PLLs). In order to reduce the output jitter, several strategies are presented, which are suitable for high speed PLL design. The thesis is organized as six chapters. The first chapter is the introduction. In chapter 2, the background knowledge for the PLL design is overviewed. In chapter 3, a PLL with multi-phase control architecture is proposed. Since the proposed architecture effectively suppresses the ripple of the controlled voltage, the jitter resulted from the reference feedthrough is decreased. The circuit is implemented with 0.18-μm CMOS technologies and the measured resulted is also included in this chapter. In chapter 4, a PLL with a compact loop filter is presented. The presented architecture is well suited for the implementation of fully integrated PLLs since the required capacitance in the loop filter can be substantially reduced. The jitter performance will be improved because of the absence of offchip components. The circuit is also realized with 0.18-μm CMOS process and the measured resulted is also included in this chapter. In chapter 5, a PLL operated at 30-GHz is designed and simulated. The modified Colpitts VCO is adopted for the reduction of the VCO noise. A regenerative frequency divider is also employed to widen the dividable range at such high frequency. The design process and the simulation results will be illustrated in this chapter. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/9519 |
全文授權: | 同意授權(全球公開) |
顯示於系所單位: | 電子工程學研究所 |
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ntu-97-1.pdf | 1.44 MB | Adobe PDF | 檢視/開啟 |
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