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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 邱雅萍 | zh_TW |
| dc.contributor.advisor | Ya-Ping Chiu | en |
| dc.contributor.author | 曾楷崴 | zh_TW |
| dc.contributor.author | Kai-Wei Tseng | en |
| dc.date.accessioned | 2024-08-15T16:31:44Z | - |
| dc.date.available | 2024-08-16 | - |
| dc.date.copyright | 2024-08-15 | - |
| dc.date.issued | 2024 | - |
| dc.date.submitted | 2024-08-07 | - |
| dc.identifier.citation | [1] A. Liu et al., "The Roadmap of 2D Materials and Devices Toward Chips," Nano-Micro Letters, vol. 16, no. 1, p. 119, 2024.
[2] M. C. Lemme, D. Akinwande, C. Huyghebaert, and C. Stampfer, "2D materials for future heterogeneous electronics," Nature communications, vol. 13, no. 1, p. 1392, 2022. [3] J. Strachan, A. F. Masters, and T. Maschmeyer, "3R-MoS2 in review: history, status, and outlook," ACS Applied Energy Materials, vol. 4, no. 8, pp. 7405-7418, 2021. [4] K. Liu et al., "A wafer-scale van der Waals dielectric made from an inorganic molecular crystal film," Nature Electronics, vol. 4, no. 12, pp. 906-913, 2021. [5] Y. Xu et al., "Scalable integration of hybrid high-κ dielectric materials on two-dimensional semiconductors," Nature Materials, vol. 22, no. 9, pp. 1078-1084, 2023. [6] L. Liu, K. Liu, and T. Zhai, "Emerging van der Waals Dielectrics of Inorganic Molecular Crystals for 2D Electronics," ACS nano, 2024. [7] B. Zheng and Y. Chen, "Controllable growth of monolayer MoS2 and MoSe2 crystals using three-temperature-zone furnace," in IOP conference series: materials science and engineering, 2017, vol. 274, no. 1: IOP Publishing, p. 012085. [8] J. Xi, X. Huang, M. Hu, and W. Xiang, "Dependence of laser parameters on structural properties of pulsed laser-deposited MoS 2 thin films applicable for field effect transistors," Journal of Materials Science: Materials in Electronics, vol. 31, pp. 21118-21127, 2020. [9] B. Radisavljevic, M. B. Whitwick, and A. Kis, "Integrated circuits and logic operations based on single-layer MoS2," ACS nano, vol. 5, no. 12, pp. 9934-9938, 2011. [10] X. Cui et al., "Multi-terminal transport measurements of MoS2 using a van der Waals heterostructure device platform," Nature nanotechnology, vol. 10, no. 6, pp. 534-540, 2015. [11] M.-L. Chen et al., "A FinFET with one atomic layer channel," Nature communications, vol. 11, no. 1, p. 1205, 2020. [12] X. Wang, C. Liu, Y. Wei, S. Feng, D. Sun, and H. Cheng, "Three-dimensional transistors and integration based on low-dimensional materials for the post-Moore’s law era," Materials Today, vol. 63, pp. 170-187, 2023. [13] X. Huang et al., "High drive and low leakage current MBC FET with channel thickness 1.2 nm/0.6 nm," in 2020 IEEE International Electron Devices Meeting (IEDM), 2020: IEEE, pp. 12.1. 1-12.1. 4. [14] Y.-W. Lan et al., "Scalable fabrication of a complementary logic inverter based on MoS 2 fin-shaped field effect transistors," Nanoscale Horizons, vol. 4, no. 3, pp. 683-688, 2019. [15] P. Zhao et al., "Evaluation of border traps and interface traps in HfO2/MoS2 gate stacks by capacitance–voltage analysis," 2D Materials, vol. 5, no. 3, p. 031002, 2018. [16] L. E. Aygun, F. B. Oruc, F. B. Atar, and A. K. Okyay, "Dynamic control of photoresponse in zno-based thin-film transistors in the visible spectrum," IEEE Photonics Journal, vol. 5, no. 2, pp. 2200707-2200707, 2013. [17] T. Mangla, A. Sehgal, M. Saxena, S. Haldar, M. Gupta, and R. Gupta, "Optimization of gate stack MOSFETs with quantization effects," JSTS: Journal of Semiconductor Technology and Science, vol. 4, no. 3, pp. 228-239, 2004. [18] N. Alfaraj, "Reversibly Bistable Flexible Electronics," 2015. [19] M. Sun, D. Xie, Y. Sun, W. Li, C. Teng, and J. Xu, "Lateral multilayer/monolayer MoS2 heterojunction for high performance photodetector applications," Scientific reports, vol. 7, no. 1, p. 4505, 2017. [20] S. Samanta et al., "Low subthreshold swing and high mobility amorphous indium–gallium–zinc-oxide thin-film transistor with thin HfO 2 gate dielectric and excellent uniformity," IEEE Electron Device Letters, vol. 41, no. 6, pp. 856-859, 2020. [21] T. A. Fjeldly, M. Shur, and T. Ytterdal, Introduction to device modeling and circuit simulation. John Wiley & Sons, Inc., 1997. [22] C. Jung et al., "Highly crystalline CVD-grown multilayer MoSe2 thin film transistor for fast photodetector," Scientific reports, vol. 5, no. 1, p. 15313, 2015. [23] R. Voo, M. Mariatti, and L. Sim, "Properties of epoxy nanocomposite thin films prepared by spin coating technique," Journal of Plastic Film & Sheeting, vol. 27, no. 4, pp. 331-346, 2011. [24] P.-C. Chen et al., "Effective N-methyl-2-pyrrolidone wet cleaning for fabricating high-performance monolayer MoS 2 transistors," Nano Research, vol. 12, pp. 303-308, 2019. [25] L. Yang et al., "Chloride molecular doping technique on 2D materials: WS2 and MoS2," Nano letters, vol. 14, no. 11, pp. 6275-6280, 2014. [26] P.-C. Shen et al., "Ultralow contact resistance between semimetal and monolayer semiconductors," Nature, vol. 593, no. 7858, pp. 211-217, 2021. [27] J. Lin et al., "High-current MoS2 transistors with non-planar gate configuration," Science Bulletin, vol. 66, no. 8, pp. 777-782, 2021. [28] W. Li et al., "Uniform and ultrathin high-κ gate dielectrics for two-dimensional electronic devices," Nature Electronics, vol. 2, no. 12, pp. 563-571, 2019. [29] P. Luo et al., "Molybdenum disulfide transistors with enlarged van der Waals gaps at their dielectric interface via oxygen accumulation," Nature Electronics, vol. 5, no. 12, pp. 849-858, 2022. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/94267 | - |
| dc.description.abstract | 由於傳統介電材料如氧化鋁(Al2O3)和二氧化矽(SiO2)具有較高的熔點，直接通過熱蒸鍍在二維材料上沉積氧化層可能會導致破壞。因此，三氧化二銻(Sb2O3)由於其獨特的材料性質，可以作為二硫化鉬(MoS2)場效電晶體的閘極氧化層。三氧化二銻具有高介電常數(11.5)，其分子間透過凡德瓦力相互結合，在高真空(10-6 Torr)條件下於186℃昇華。三氧化二銻分子是雙環籠(bicyclic cage)結構，且無懸鍵結構，與二硫化鉬在界面處形成凡德瓦接觸，相較於傳統的氧化層提供了更卓越的介電性能。
在本研究中，該元件在室溫(T= 298K)下的上閘極(VTG)工作範圍為±1 V。最大汲極-源極電流(IDS)為0.21 µA，並展示出高達106的開關比。此元件的臨界電壓(VTH)為0.0088 V，次臨界擺幅(SS)為86.1 mV/dec，載子遷移率為13.5 cm2/Vs，遲滯為24mV。在常關態(normally-off state)的元件中，施加+8V的背閘極(VBG)，變為常開態(normally-on state)，IDS為0.74 µA，相比於常關態，載子遷移率提升355倍，遲滯僅為6.51mV。所有性能均具有高度競爭力，代表了在二維材料CMOS元件發展方面有顯著進步。 | zh_TW |
| dc.description.abstract | Due to the high melting point for the conventional dielectric material such as aluminum oxide (Al2O3) and silicon dioxide (SiO2), depositing oxide layers on two-dimensional materials directly via thermal evaporator may lead to damage. Therefore, antimony trioxide (Sb2O3), a high dielectric constant (11.5) material, can be the oxide layer in molybdenum disulfide (MoS2) field-effect transistors because of its unique material properties which molecules are bonded by van der Waals force and sublime at 186℃ in high vacuum (10-6 Torr) condition. Sb2O3 molecules are bicyclic cage structure which is free-dangling bond and form van der Waals contacts with MoS2 at the interface, offering superior performance compared to conventional oxide layers.
In this study, the device has an applied range of ±1V for top gate (VTG) at room temperature (T = 298K). The maximum drain-source current (IDS) is 0.21 µA, and it exhibits a high on/off ratio of up to 106. The threshold voltage (VTH) for this device is 0.0088 V, the subthreshold swing (SS) is 86.1 mV/dec, the carrier mobility is 13.5 cm²/Vs and hysteresis is 24 mV. In a normally-off device, applying +8V to the back gate (VBG) switches it to a normally-on state. The IDS reaches 0.74 µA, which carrier mobility is 355 times larger than normally-off state, with a hysteresis of only 6.51 mV. All the performance are highly competitive, which represents significant progress in the development of two-dimensional material CMOS devices. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2024-08-15T16:31:44Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2024-08-15T16:31:44Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 致謝 i
摘要 ii Abstract iii 目錄 iv 圖目錄 vii 表目錄 x 1 第一章 緒論 1 1.1 二維材料的發展與應用 1 1.2 二硫化鉬材料特性 3 1.3 三氧化二銻材料特性 4 1.4 研究動機 5 2 第二章 理論與文獻回顧 6 2.1 二硫化鉬之材料分析 6 2.1.1 拉曼光譜學 (Raman Spectroscopy) 6 2.1.2 光致發光光譜學 (Photoluminescence Spectroscopy, PL) 7 2.1.3 掃描電子顯微鏡(Scanning Electron Microscope, SEM) 8 2.1.4 聚焦離子束顯微鏡(Focused Ion Beam, FIB) 9 2.1.5 穿透式電子顯微鏡(Transmission Electron Microscope, TEM) 9 2.1.6 X光光電子能譜 (X-ray photoelectron spectroscopy, XPS) 10 2.1.7 原子力顯微鏡 (Atomic Force Microscope) 11 2.2 二硫化鉬電晶體元件設計 11 2.2.1 電晶體特性 (Transistor) 11 2.2.2 歐姆接觸量測原理(Ohmic Contact) 13 2.3 元件電性分析與參數 14 2.3.1 電容電壓量測法 (Capacitance-Voltage measurement) 14 2.3.2 電流開關比(Current on/off-ratio, Ion/Ioff) 15 2.3.3 臨界電壓(Threshold Voltage, VTH) 16 2.3.4 場效遷移率(Field-Effect Mobility, µ) 17 2.3.5 次臨界擺幅(Subthreshold Swing, SS) 18 2.3.6 汲極引起能障降低(Drain-induced Barrier Lowering, DIBL) 19 3 第三章 實驗儀器介紹 21 3.1 製程儀器(Process Equipment) 21 3.1.1 化學氣相沉積(Chemical Vapor Deposition, CVD) 21 3.1.2 旋轉塗佈機(Spin Coater) 22 3.1.3 微影系統(Lithography System) 23 3.1.4 電漿蝕刻機 (Plasma Etching Machine) 23 3.1.5 熱蒸鍍機(Thermal Evaporator) 24 3.1.6 電性量測系統 (Electrical Measurement System) 24 3.2 製程流程 (Process Flow) 25 3.2.1 二硫化鉬直接成長 (Directly Growth) 25 3.2.2 製作標準晶片 (Standard Chip Fabrication) 25 3.2.3 濕式轉移二硫化鉬 (Wet Transfer) 27 3.2.4 圖案設計 (Pattern Design) 28 3.2.5 電極製作 (Electrode Fabrication) 29 4 第四章 結果與討論 32 4.1 材料分析結果 (Material Analysis) 32 4.1.1 拉曼光譜學分析 (Raman Spectrum Analysis) 32 4.1.2 光致發光光譜學分析 (PL Spectrum Analysis) 34 4.1.3 X射線光電子能譜分析 (XPS Analysis) 35 4.2 三氧化二銻特性分析 (Antimony Trioxide Analysis) 37 4.3 二硫化鉬場效電晶體特性分析(MoS2 FETs Analysis) 44 4.3.1 場效電晶體電性量測 (FETs Measurement) 44 4.4 二硫化鉬雙閘極場效電晶體特性分析(MoS2 Dual-gated FETs Analysis) 47 4.4.1 上閘極電性量測 (Top-gated Measurement) 47 4.4.2 背閘極電性量測 (Back-gated Measurement) 52 4.4.3 雙閘極調控—上閘極電性量測 (Dual-gated Controls – Top-gated Measurement) 54 4.4.4 雙閘極調控—背閘極電性量測 (Dual-gated Controls – Back-gated Measurement) 60 4.4.5 雙閘極場效電晶體優點與缺點 (Pros and Cons) 61 4.5 上閘極場效電晶體電性比較 (Comparison of Top-gated FETs Electrical Performance) 63 5 第五章 結論與未來展望 65 6 參考文獻 66 | - |
| dc.language.iso | zh_TW | - |
| dc.subject | 高介電材料 | zh_TW |
| dc.subject | 雙閘極場效電晶體 | zh_TW |
| dc.subject | 凡德瓦接觸 | zh_TW |
| dc.subject | 二維材料 | zh_TW |
| dc.subject | Two-dimensional material | en |
| dc.subject | Dual gate field-effect transistors | en |
| dc.subject | van der Waals contact | en |
| dc.subject | High-κdielectric material | en |
| dc.title | 高性能凡德瓦高介電材料雙閘極二硫化鉬場效電晶體 | zh_TW |
| dc.title | High Performance of Dual-gated Molybdenum Disulfide Field Effect Transistor Enabled by van der Waals High-κ Dielectric Material | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 112-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.coadvisor | 藍彥文 | zh_TW |
| dc.contributor.coadvisor | Yann-Wen Lan | en |
| dc.contributor.oralexamcommittee | 蘇清源;柯忠廷 | zh_TW |
| dc.contributor.oralexamcommittee | Ching-Yuan Su;Chung-Ting Ke | en |
| dc.subject.keyword | 二維材料,高介電材料,凡德瓦接觸,雙閘極場效電晶體, | zh_TW |
| dc.subject.keyword | Two-dimensional material,High-κdielectric material,van der Waals contact,Dual gate field-effect transistors, | en |
| dc.relation.page | 68 | - |
| dc.identifier.doi | 10.6342/NTU202402946 | - |
| dc.rights.note | 未授權 | - |
| dc.date.accepted | 2024-08-10 | - |
| dc.contributor.author-college | 重點科技研究學院 | - |
| dc.contributor.author-dept | 奈米工程與科學學位學程 | - |
| 顯示於系所單位： | 奈米工程與科學學位學程 | |
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