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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 吳肇欣 | zh_TW |
| dc.contributor.advisor | Chao-Hsin Wu | en |
| dc.contributor.author | 何驊凌 | zh_TW |
| dc.contributor.author | HUA-LING HO | en |
| dc.date.accessioned | 2024-08-09T16:34:16Z | - |
| dc.date.available | 2024-08-10 | - |
| dc.date.copyright | 2024-08-09 | - |
| dc.date.issued | 2024 | - |
| dc.date.submitted | 2024-08-02 | - |
| dc.identifier.citation | [1] Y. Manin, “Computable and Uncomputable,” Sovetskoye Radio Press, Moscow, 1980.
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/93940 | - |
| dc.description.abstract | 近年來，量子計算因其卓越的計算能力而受到廣泛關注，相較傳統計算機能更快、更高效地解決複雜的問題。對於大規模量子計算機來說，超導和半導體量子位元被認為是最有前途的候選者，因為它們與VLSI兼容。然而，由於它們需要在低溫下操作，因此室溫電子儀器控制和讀取量子位元會限制數量的擴展。因此，低溫電路的存在是必須的，以減少信號失真、延遲、以及導線上的熱梯度等問題。此外，為了準確設計符合低溫電路需求的電路，需要一個適用於低溫(至4 K)操作的低溫CMOS的SPICE模型。
本論文創建一個40-nm CMOS電晶體、適用溫度為300 K到4 K的SPICE模型。首先，提取了寄生電容，如Cgb、Cgc和Cgg，以利於交流訊號建模。隨後，使用Calibre軟體實現了佈局參數過濾，可以消除由於不同測試元件佈局(例如LOD和WPE)導致的製程變化。最後，使用Utmost軟體對測量數據進行BSIM4模型擬合。在300到4 K的溫度範圍內，擬合的I-V和C-V曲線與實驗結果非常吻合。 接著，展示了一個用於量子位元控制電路的20 GHz驅動放大器設計。使用ADS軟體對40-nm CMOS進行了RF特性的模擬。為了達到優異的線性和功率效率，選擇了AB類放大器。透過採用疊接共源極組態配置來增強增益，並利用源極電感和電阻自偏壓負回授機制來確保穩定性。最後進行電磁模擬，以取得能夠達到最小損耗和最高穩定性的被動元件設計。根據模擬結果顯示，在20 GHz時，增益參數S21為15.2 dB，3 dB頻帶寬為8.2 GHz。輸入功率為-10 dBm時，輸出功率1 dB壓縮點約為3 dBm，而最大功率附加效率(PAE)達到26.2%，與設計目標一致。 | zh_TW |
| dc.description.abstract | In recent years, quantum computing has gained much attention for its immense computational power, cability of solving complex problems exponentially faster and more efficiently than classical computing. For large-scale quantum computers, superconducting and semiconductor qubits are considered the most promising candidates owing to their VLSI compatibility. However, since they need to be operated at cryogenic temperatures, control and readout of qubits by room-temperature electronic instrument prohibits future scaling. Therefore, control/readout circuits operated at cryogenic temperatures are necessary to mitigate issues such as signal distortion, latency, thermal gradient along the wiring, etc. For accurate circuit design to meet the requirements of cryogenic circuits, a SPICE model of cryo-CMOS suitable for the operation at cryogenic temperatures (down to 4 K) is required.
This thesis focuses on creating a SPICE model for 40-nm CMOS devices at 300 K ~ 4 K. First, parasitic capacitances such as Cgb, Cgc, and Cgg are extracted for ac circuits. Subsequently, the process coefficient filtering of the layout is achieved using the Calibre software to remove process variations due to different layouts of test-keys, for example, LOD and WPE. Finally, using the Utmost software, the measured data are processed for BSIM4 model fitting. Fitting I-V and C-V curves match to the experimental results very well at temperatures of 300 ~ 4 K. Next, a design of 20-GHz driver for the control circuit of quantum bits is demonstrated. Simulations of RF characteristics are conducted using the ADS software for 40-nm CMOS technology. For excellent linearity and power efficiency, a class AB amplifier is selected. A cascode common-source configuration is adopted for gain enhancement, while stability is ensured through a source inductance and resistive self-bias feedback mechanism. Electromagnetic simulations are performed to identify the critical passive components to achieve minimal loss and highest stability. The simulation results show a gain parameter S21 of 15.2 dB at 20 GHz with a 3 dB bandwidth of 8.2 GHz. The output-power 1-dB compression point is approximately 3 dBm for an input power of -10 dBm, and the maximum Power Added Efficiency (PAE) reaches 26.2%, consistent with the design objectives. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2024-08-09T16:34:16Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2024-08-09T16:34:16Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 口試委員會審定書 i
誌謝 ii 摘要 iii Abstract iv 目次 vi 圖次 viii 表次 xv 第 1 章 量子計算 1 1.1 引言 1 1.2 量子位元處理器 2 1.3 量子處理器的控制/讀取介面 6 1.4 論文架構 9 第 2 章 電晶體之低溫SPICE模型 11 2.1 Cryo-CMOS物理機制 11 2.2 測試元件的量測與分析 15 2.2.1 電晶體元件電容量測架構 15 2.2.2 閘極到基板的電容Cgb 16 2.2.3 閘極到汲極/源極的電容Cgc 22 2.2.4 閘極到汲極/源極/基底的電容Cgg 26 2.2.5 低溫量測結果 31 2.3 元件模型擬合 35 2.3.1 建立結構模型 35 2.3.2 電晶體固生、寄生電容擬合 40 2.4 結論 48 第 3 章 低溫功率放大器之設計 49 3.1 量子位元的操控電路介面 49 3.1.1 鎖相迴路 49 3.1.2 數字控制振盪器 52 3.1.3 數位類比轉換器 54 3.1.4 混頻器和功率放大器 56 3.2 功率放大器 58 3.2.1 線性度 58 3.2.2 功率效率 62 3.3 功率放大器的電路設計 66 3.3.1 規格與功率預算 66 3.3.2 偏壓與電晶體尺寸選擇 68 3.3.3 負載拉移分析 75 3.3.4 輸出和輸入的匹配網路設計 78 3.3.5 被動元件佈局設計 80 3.4 模擬結果 87 3.5 結論 90 第 4 章 結論及未來工作 91 4.1 結論 91 4.2 未來工作 91 參考文獻 93 | - |
| dc.language.iso | zh_TW | - |
| dc.subject | 低溫電晶體 | zh_TW |
| dc.subject | 電磁模擬 | zh_TW |
| dc.subject | SPICE 模型 | zh_TW |
| dc.subject | 量子計算 | zh_TW |
| dc.subject | Quantum computing | en |
| dc.subject | Electromagnetic simulation | en |
| dc.subject | SPICE model | en |
| dc.subject | cryo-CMOS | en |
| dc.title | 低溫電晶體元件的 SPICE 模型於量子計算之應用 | zh_TW |
| dc.title | SPICE modeling of cryo-CMOS devices for quantum computing | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 112-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.coadvisor | 李峻霣 | zh_TW |
| dc.contributor.coadvisor | Jiun-Yun Li | en |
| dc.contributor.oralexamcommittee | 卓大鈞;柯鈞琳 | zh_TW |
| dc.contributor.oralexamcommittee | Da-Jun Zhuo;Jun-Lin Ke | en |
| dc.subject.keyword | 量子計算,低溫電晶體,SPICE 模型,電磁模擬, | zh_TW |
| dc.subject.keyword | Quantum computing,cryo-CMOS,SPICE model,Electromagnetic simulation, | en |
| dc.relation.page | 101 | - |
| dc.identifier.doi | 10.6342/NTU202403186 | - |
| dc.rights.note | 未授權 | - |
| dc.date.accepted | 2024-08-06 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 光電工程學研究所 | - |
| 顯示於系所單位： | 光電工程學研究所 | |
文件中的檔案：
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-112-2.pdf 未授權公開取用 | 8.27 MB | Adobe PDF |
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