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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/93513完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 林宗賢 | zh_TW |
| dc.contributor.advisor | Tsung-Hsien Lin | en |
| dc.contributor.author | 李嵦豐 | zh_TW |
| dc.contributor.author | Kai-Feng Lee | en |
| dc.date.accessioned | 2024-08-05T16:18:04Z | - |
| dc.date.available | 2024-08-06 | - |
| dc.date.copyright | 2024-08-05 | - |
| dc.date.issued | 2024 | - |
| dc.date.submitted | 2024-07-16 | - |
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/93513 | - |
| dc.description.abstract | 在本論文中提出了一種基於轉導電容式積分器和壓控振盪器的二階電容耦合連續時間Δ-Σ調製器，用於閉環神經記錄傳感器讀取。
這種方法消除了在前端電路中使用低雜訊放大器和類比數位轉換器的需求。而是直接透過使用高解析度的Δ-Σ調變器當作完整的感測器前端電路。並通過在第二級使用壓控振盪器作為量化器，經過動態元素匹配處理後的數位輸出增加了數位類比轉換器的線性度，從而無需傳統的動態單元匹配電路。第一級積分器使用了具有轉導增強的轉導電容式積分器，提供良好的線性度和低噪音性能。 此外，由於製程變異導致的電晶體不匹配和低頻雜訊的影響，這些原因會導致信號品質被影響並增加設計的困難，因此本設計使用斬 波器來緩解低頻雜訊以及電晶體不匹配的問題。此外在回授迴路中加入數位濾波器有助於減輕因使用斬波器而導致的量化噪音混疊的問題，且在不犧牲系統線性度的情況可以使用較少振盪器級數。 該晶片採用TSMC 180-nm CMOS製程。本讀取電路在10kHz頻寬下達到83.61dB的訊噪及失真比和84.06dB的動態範圍，功耗為83.64W（類比電壓1.8V，數位電壓1.2V），該晶片的面積為0.775mm2。且此電路的品質因素達到164.4dB。 | zh_TW |
| dc.description.abstract | This dissertation presents a second-order capacitively-coupled continuous-time delta-sigma modulator (CTDSM) based on a Gm-C integrator and voltage-controlled oscillator (VCO) for closed-loop neural recording sensor readout.
This approach eliminates the need for a low-noise IA and an ADC in the front end. Instead, a high-resolution DSM serves as the entire sensing front-end. By utilizing the voltage-controlled oscillator in the second stage as a quantizer, the digital output, after dynamic element matching, enhances the digital-to-analog converter's linearity. This obviates the need for conventional dynamic element matching circuits. The first-stage integrator employs a Gm-C integrator with Gm-boosting, providing excellent linearity and low noise performance. Furthermore, because DC offset and flicker noise fall within the low-frequency range, signal quality is compromised, raising design complexity. This work uses a chopper to tackle these issues. Additionally, incorporating a FIR filter in the feedback loop helps mitigate the issue of quantization noise aliasing caused by the use of a chopper, and allows for the use of fewer oscillator stages without sacrificing system linearity. The chip is fabricated in the TSMC 0.18-μm CMOS process. The prototype readout circuit achieves 83.61dB SNDR in 10kHz bandwidth and 84.06dB dynamic range, consuming 83.64W (VDDA = 1.8, VDDD = 1.2) and 0.775mm2 active area. The sensor readout achieves FoMs of 164.4dB. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2024-08-05T16:18:04Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2024-08-05T16:18:04Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 論文口試委員會審定書 i
摘要 v Abstract vii List of Figures xi List of Tables xvi Chapter 1 Introduction 1 1.1 Background 1 1.2 Dissertation Overview 2 Chapter 2 Fundamental of Neural Recording Interface Circuits and Prior Art 3 2.1 Basic Sensor Read-Out Systems 3 2.2 Neural Interface System Introduction and Non-Idealities 5 2.2.1 Stimulation Artifact 5 2.2.2 The Stimulation Artifact Mitigation Techniques 7 2.3 Non-Idealities in Electrode 9 2.3.1 Offset Voltage 9 2.3.2 Noise Response 10 2.4 State-of-the-art Neural Interface Circuit 12 2.4.1 IA and CTDSM 13 2.4.2 Open Loop VCO-Based ADC 16 2.4.3 Closed Loop VCO-Based ADC 18 2.4.4 Front-End Embedded VCO-Based CTDSM 21 Chapter 3 Introduction of Voltage-Controlled Oscillator based Quantizer and Integrator 24 3.1 Fundamentals of VCO-based Integrators 24 3.2 VCO-Based Integrator 27 3.2.1 Difference between the Gm-C Integrator and VCO-Based Integrator 27 3.2.2 Operation of VCO-based Integrator 29 3.3 VCO-Based Quantizer 31 3.3.1 Noise-Shaped Integrating Quantizer 31 3.3.2 FDC VCO-Based Quantizer 32 3.3.3 Dynamic Element Matching by FDC VCO-Based quantizer 36 Chapter 4 Design of a Capacitively Coupled 2nd-order CTDSM with VCO-based Quantizer 38 4.1 Introduction 38 4.2 System Architecture 42 4.2.1 Motivation 42 4.2.2 The Block Diagram and Architecture of The Proposed System 43 4.2.3 Behavior Model Simulation 47 4.3 Building Blocks 52 4.3.1 First Stage Gm-C Integrator 52 4.3.2 Chopper Induced Quantization Noise Aliasing 62 4.3.3 Guard Time Switch 64 4.3.4 Proposed Finite Impulse Response Filter CDAC 67 4.3.5 Second Stage Gm-CCO and FDC Quantizer 69 4.4 System Simulation Results 75 Chapter 5 Experimental Result of the 2nd-order CCO-based CTDSM 77 5.1 Die Photo 77 5.2 Measurement Environment Setup 77 5.3 PCB Board 78 5.4 Measurement Result 80 5.4.1 Output Spectrum Analyze 80 5.4.2 Dynamic Range and Linearity 82 5.4.3 Common Mode Rejection Ratio 84 5.4.4 Power Measurement Result and Comparison Table 86 5.5 Discussion and Summary 87 Chapter 6 Conclusions and Future Works 89 6.1 Conclusions 89 6.2 Future Works 90 References 91 | - |
| dc.language.iso | en | - |
| dc.subject | 感測器 | zh_TW |
| dc.subject | 類比數位轉換器 | zh_TW |
| dc.subject | 斬波器 | zh_TW |
| dc.subject | 有限脈衝響應濾波器 | zh_TW |
| dc.subject | 腦波偵測 | zh_TW |
| dc.subject | 類比前端電路 | zh_TW |
| dc.subject | 環形振盪器 | zh_TW |
| dc.subject | Analog Front-End (AFE) | en |
| dc.subject | Chopper | en |
| dc.subject | Analog to Digital Converter (ADC) | en |
| dc.subject | Ring Oscillator | en |
| dc.subject | Neural Recording | en |
| dc.subject | Sensor | en |
| dc.subject | FIR Filter | en |
| dc.title | 一個使用有限脈衝響應濾波器回授之13.6有效位元基於電壓控制振盪器之二階連續時間三角積分調變器 | zh_TW |
| dc.title | Design of a 13.6-bit ENOB VCO-Based 2nd-order CTDSM with FIR Feedback | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 112-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 鍾勇輝;李泰成;劉深淵;許雲翔 | zh_TW |
| dc.contributor.oralexamcommittee | Yung-Hui Chung;Tai-Cheng Lee;Shen-Iuan Liu;Yun-Shiang Shu | en |
| dc.subject.keyword | 感測器,類比前端電路,腦波偵測,環形振盪器,類比數位轉換器,斬波器,有限脈衝響應濾波器, | zh_TW |
| dc.subject.keyword | Sensor,Analog Front-End (AFE),Neural Recording,Ring Oscillator,Analog to Digital Converter (ADC),Chopper,FIR Filter, | en |
| dc.relation.page | 97 | - |
| dc.identifier.doi | 10.6342/NTU202401734 | - |
| dc.rights.note | 同意授權(限校園內公開) | - |
| dc.date.accepted | 2024-07-17 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| dc.date.embargo-lift | 2029-07-14 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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