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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/93424完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 呂良鴻 | zh_TW |
| dc.contributor.advisor | Liang-Hung Lu | en |
| dc.contributor.author | 張文豪 | zh_TW |
| dc.contributor.author | Wen-Hao Chang | en |
| dc.date.accessioned | 2024-07-31T16:15:35Z | - |
| dc.date.available | 2024-08-01 | - |
| dc.date.copyright | 2024-07-31 | - |
| dc.date.issued | 2024 | - |
| dc.date.submitted | 2024-06-03 | - |
| dc.identifier.citation | [1] L. Kong and B. Razavi, “A 2.4 GHz 4 mW Integer-N Inductorless RF Synthesizer,” IEEE Journal of Solid-State Circuits, vol. 51, no. 3, pp. 626–635, 2016.
[2] B. Razavi, Design of analog CMOS integrated circuits. Tsinghua University Press Co., Ltd., 2005. [3] A. Grebene and H. Camenzind, “Phase locking as a new approach for tuned integrated circuits,” in 1969 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, vol. XII, 1969, pp. 100–101. [4] A. Sharkia, S. Mirabbasi, and S. Shekhar, “A Type-I Sub-Sampling PLL With a 100 × 100 μm2 Footprint and 255-dB FOM,” IEEE Journal of Solid-State Circuits, vol. 53, no. 12, pp. 3553–3564, 2018. [5] H. Rategh, H. Samavati, and T. Lee, “A CMOS frequency synthesizer with an injection-locked frequency divider for a 5-GHz wireless LAN receiver,” IEEE Journal of Solid-State Circuits, vol. 35, no. 5, pp. 80–787, 2000. [6] P. Hanumolu, M. Brownlee, K. Mayaram, and U.-K. Moon, “Analysis of charge-pump phase-locked loops,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 51, no. 9, pp. 1665–1674, 2004. [7] R. Gu, A.-L. Yee, Y. Xie, and W. Lee, “A 6.25GHz 1V LC-PLL in 0.13/spl mu/m CMOS,” in 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers, 2006, pp. 2442–2451. [8] T. Wu, P. K. Hanumolu, K. Mayaram, and U.-K. Moon, “A 4.2 GHz PLL Frequency Synthesizer with an Adaptively Tuned Coarse Loop,” in 2007 IEEE Custom Integrated Circuits Conference, 2007, pp. 547–550. [9] S. P. Bruss and R. R. Spencer, “A 5GHz CMOS PLL with low KVCO and extended fine-tuning range,” in 2008 IEEE Radio Frequency Integrated Circuits Symposium, 2008, pp. 669–672. [10] B. C ̧ atlı, A. Nazemi, T. Ali, S. Fallahi, Y. Liu, J. Kim, M. Abdul-Latif, M. R. Ahmadi, H. Maarefi, A. Momtaz, and N. Kocaman, “A Sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications,” in Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013, pp. 1–4. [11] F. Gardner, “Charge-Pump Phase-Lock Loops,” IEEE Transactions on Communications, vol. 28, no. 11, pp. 1849–1858, 1980. [12] F. Song, Y. Zhao, B. Wu, L. Tang, L. Lin, and B. Razavi, “16.5 A Fractional-N Synthesizer with 110fsrms Jitter and a Reference Quadrupler for Wideband 802.11ax,” in 2019 IEEE International Solid-State Circuits Conference - (ISSCC), 2019, pp. 264–266. [13] S.-Y. Cho, S. Kim, M.-S. Choo, J. Lee, H.-G. Ko, S. Jang, S.-H. Chu, W. Bae, Y. Kim, and D.-K. Jeong, “A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection,” in ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC), 2015, pp. 384–387. [14] B. Razavi, Design of CMOS phase-locked loops: from circuit level to architecture level. Cambridge University Press, 2020. [15] S. Shekhar, Wideband frequency synthesizers. University of Washington, 2008. [16] B. Razavi, “Principles of data conversion system design,” (No Title), 1994. [17] Y. Sun, J. Li, Z. Zhang, M. Wang, N. Xu, H. Lv, W. Rhee, Y. Li, and Z. Wang, “A 2.74–5.37GHz boosted-gain type-I PLL with ¡152012 IEEE Radio Frequency Integrated Circuits Symposium, 2012, pp. 181–184. [18] A. Sharkia, S. Aniruddhan, S. Mirabbasi, and S. Shekhar, “A Compact, Voltage-Mode Type-I PLL With Gain-Boosted Saturated PFD and Synchronous Peak Tracking Loop Filter,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 1, pp. 43–53, 2019. [19] R. K. Nandwana, T. Anand, S. Saxena, S.-J. Kim, M. Talegaonkar, A. Elkholy, W.-S. Choi, A. Elshazly, and P. K. Hanumolu, “A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method,” IEEE Journal of Solid-State Circuits, vol. 50, no. 4, pp. 882–895, 2015. [20] A. Sai, T. Yamaji, and T. Itakura, “A 570fsrms integrated-jitter ring-VCO-based 1.21GHz PLL with hybrid loop,” 2011 IEEE International Solid-State Circuits Conference, pp. 98–100, 2011. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/93424 | - |
| dc.description.abstract | 在當今的多頻多模通信系統中，一個體積小巧、靈活性高且具有高頻譜純度的時脈產生器是不可或缺的。由於其穩定性高、佔用空間小，第一類鎖相迴路(Type-I PLL) 近來已成為許多研究的焦點。然而，第一類鎖相迴路的鎖定範圍受到限制，這不僅使得其在實際應用中無法確保在製程、電壓、溫度變異下仍能成功鎖定，也限制了其作為寬調變範圍(tuning range)時脈產生器的應用。
本論文提出了一個頻帶選擇機制並設計了相應的頻帶選擇迴路。該迴路防止了第一類鎖相迴路脫鎖，並克服了鎖定範圍和參考突波之間的取捨。藉由頻帶選擇迴路的輔助，本論文實現了一個寬調變範圍的第一類鎖相迴路。該晶片採用TSMC 180-nm CMOS 製程實現，核心電路面積為0.12 mm2，操作電壓為1.8 V，輸出頻率範圍為840 - 2240 MHz，提供了超過90%的調變範圍。當輸入參考頻率為10 MHz，輸出頻率為2240 MHz 時，在1-MHz 頻率偏移的地方，相位雜訊為-91.7 dBc/Hz，參考突波為-50 dBc。在論文的最後，對該晶片進行了優化，計算出了最佳化的參數設計及系統頻率規劃。 此外，本文提出的頻帶選擇迴路易於適應不同的製程，並有望在未來與基於單元(cell-based)的設計流程結合，以簡化設計複雜性。 | zh_TW |
| dc.description.abstract | In today’s multi-band and multi-mode communication systems, a compact, flexible, and high-spectral purity clock generator is indispensable. Due to its high stability and small footprint, the type-I PLL has recently become the focus of much research. However, the acquisition range of Type-I PLLs is limited. This not only prevents them from reliably locking under process, voltage, and temperature variations in real-world applications but also restricts their use as wide-tuning range clock generators.
This paper proposes a band-selecting mechanism and designs a corresponding band-selecting loop. The loop prevents the type-I PLL from unlocking and overcomes the trade-off between the acquisition range and the reference spur. With the assistance of the band-selecting loop, this paper realizes a wide tuning range type-I PLL. The chip is implemented in a TSMC 180-nm CMOS process, with a core circuit area of 0.12 mm2, operating at 1.8 V. The output frequency range is 840 - 2240 MHz, providing over 90% of the tuning range. At an input reference frequency of 10 MHz and an output frequency of 2240 MHz, the phase noise at 1 MHz frequency offset is −91.7 dBc/Hz, and the reference spur is −50 dBc. In the final section, the optimal parameter design and system frequency planning are calculated. Furthermore, the band-selecting loop proposed in this paper is easily adaptable to different processes and is expected to be combined with cell-based design flow in the future to simplify the design complexity. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2024-07-31T16:15:35Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2024-07-31T16:15:35Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | Approval i
Acknowledgment iii Chinese Abstract v Abstract vii List of Figures xi List of Tables xv 1 Introduction 1 1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Thesis Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Introduction to Type-I PLL 5 2.1 Fundamentals of the Phase-Locked Loop . . . . . . . . . . . . . . . . . . 5 2.1.1 Voltage-Controlled Oscillators . . . . . . . . . . . . . . . . . . . 5 2.1.2 Phase Detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.3 Steady State Behavior . . . . . . . . . . . . . . . . . . . . . . . 13 2.1.4 Dynamic Behavior . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2 Transfer Function of Type-I PLL . . . . . . . . . . . . . . . . . . . . . . 16 2.3 Limitation of Acquisition Range in Type-I PLL . . . . . . . . . . . . . . 20 3 Proposed PLL 25 3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.2 Overall Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.3 Proposed Band-Selecting Loop . . . . . . . . . . . . . . . . . . . . . . . 30 3.3.1 Band-Selecting Mechanism . . . . . . . . . . . . . . . . . . . . 30 3.3.2 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.3.3 Activation of Band-Selecting Loop . . . . . . . . . . . . . . . . . 40 3.3.4 The Whole Structure of Band-Selecting Loop . . . . . . . . . . . 41 3.4 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.4.1 Phase Detector and Master-Slave Sampling Filter . . . . . . . . . 44 3.4.2 Multi-Band Voltage Control Oscillator . . . . . . . . . . . . . . . 47 3.4.3 Multi-Modulus Divider . . . . . . . . . . . . . . . . . . . . . . . 50 3.4.4 Band-Selecting Loop . . . . . . . . . . . . . . . . . . . . . . . . 58 3.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4 Experimental Results 61 4.1 Chip Photo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.2 Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.3 Experiment Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.4 Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5 Modified Design 71 5.1 Work Review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.2 Adjusted Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.3 Phase Noise Consideration . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.4 Simulation Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6 Conclusion 81 Reference 83 | - |
| dc.language.iso | en | - |
| dc.subject | 第一類 | zh_TW |
| dc.subject | 寬調變範圍 | zh_TW |
| dc.subject | 鎖定範圍 | zh_TW |
| dc.subject | 鎖相迴路 | zh_TW |
| dc.subject | Phase-Locked Loop | en |
| dc.subject | Type-I | en |
| dc.subject | Acquisition Range | en |
| dc.subject | Wide-Tuning Range | en |
| dc.title | 一個具有超寬輸出頻率範圍的CMOS 鎖相迴路 | zh_TW |
| dc.title | A CMOS Phase-Lock Loop with an Ultra-Wide Output Frequency Range | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 112-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 林宗賢;蔡宗亨 | zh_TW |
| dc.contributor.oralexamcommittee | Tsung-Hsien Lin;Tsung-Heng Tsai | en |
| dc.subject.keyword | 鎖相迴路,第一類,鎖定範圍,寬調變範圍, | zh_TW |
| dc.subject.keyword | Phase-Locked Loop,Type-I,Acquisition Range,Wide-Tuning Range, | en |
| dc.relation.page | 85 | - |
| dc.identifier.doi | 10.6342/NTU202400983 | - |
| dc.rights.note | 同意授權(全球公開) | - |
| dc.date.accepted | 2024-06-04 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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