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  1. NTU Theses and Dissertations Repository
  2. 電機資訊學院
  3. 電子工程學研究所
請用此 Handle URI 來引用此文件: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/93221
完整後設資料紀錄
DC 欄位值語言
dc.contributor.advisor陳中平zh_TW
dc.contributor.advisorChung-Ping Chenen
dc.contributor.author楊嘉恩zh_TW
dc.contributor.authorChia-En Yangen
dc.date.accessioned2024-07-23T16:21:51Z-
dc.date.available2024-07-24-
dc.date.copyright2024-07-23-
dc.date.issued2024-
dc.date.submitted2024-07-11-
dc.identifier.citation[1] N. Tang, B. Nguyen, Y. Tang, W. Hong, Z. Zhou, and D. Heo, “8.4 Fully Inte grated Buck Converter with 78 % Efficiency at 365mW Output Power Enabled by Switched­Inductor Capacitor Topology and Inductor Current Reduction Technique,” in 2019 IEEE International Solid­State Circuits Conference ­ (ISSCC), pp. 152–154, 2019.
[2] Y. Huh, S.­W. Hong, and G.­H. Cho, “A Hybrid Structure Dual­Path Step­Down Converter With 96.2 % Peak Efficiency Using 250­m Ω Large­DCR Inductor,” IEEE Journal of Solid­State Circuits, vol. 54, no. 4, pp. 959–967, 2019.
[3] A. Abdulslam and P. P. Mercier, “A Passive­Stacked Third­Order Buck Converter With Inherent Input Filtering Achieving 0.7­W/mm 2 Power Density and 94 % Peak Efficiency,” IEEE Solid­State Circuits Letters, vol. 2, no. 11, pp. 240–243, 2019.
[4] K. Hata, Y. Yamauchi, T. Sai, T. Sakurai, and M. Takamiya, “48V­to­12V Dual­Path Hybrid DC­DC Converter,” in 2020 IEEE Applied Power Electronics Conference and Exposition (APEC), pp. 2279–2284, 2020.
[5] S. Zhen, R. Yang, D. Wu, Y. Cheng, P. Luo, and B. Zhang, “Design of Hybrid Dual Path DC­DC Converter with Wide Input Voltage Efficiency Improvement,” in 2021 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5, 2021.
[6] B. Axelrod, Y. Berkovich, and A. Ioinovici, “Switched­Capacitor/Switched­Inductor Structures for Getting Transformerless Hybrid DC–DC PWM Converters,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 55, no. 2, pp. 687– 696, 2008.
[7] O. Cornea, O. Pelan, and N. Muntean, “Comparative study of buck and hybrid buck “switched­inductor"DC­DC converters,” in 2012 13th International Conference on Optimization of Electrical and Electronic Equipment (OPTIM), pp. 853–858, 2012.
[8] J. Baek, J.­H. Lee, S.­U. Shin, M.­y. Jung, and G.­H. Cho, “Switched inductor capac itor buck converter with >85 % power efficiency in 100uA­to­300mA loads using a bang­bang zero­current detector,” in 2018 IEEE Custom Integrated Circuits Con ference (CICC), pp. 1–4, 2018.
[9] W. Jung, M. Kim, H. Park, S. Yoo, T.­H. Kong, J.­H. Yang, M. Choi, J. Shin, and H.­ M. Lee, “A Hybrid Always­Dual­Path Recursive Step­Down Converter Using Adap tive Switching Level Control Achieving 95.4 % Efficiency with 288m Ω Large­DCR Inductor,” in 2022 IEEE Custom Integrated Circuits Conference (CICC), pp. 1–2, 2022.
[10] P. Gray and R. Meyer, “MOS operational amplifier design­a tutorial overview,” IEEE Journal of Solid­State Circuits, vol. 17, no. 6, pp. 969–982, 1982.
[11] B. Ahuja, “An improved frequency compensation technique for CMOS operational amplifiers,” IEEE Journal of Solid­State Circuits, vol. 18, no. 6, pp. 629–633, 1983.
[12] D. Ribner and M. Copeland, “Design techniques for cascoded CMOS op amps with improved PSRR and common­mode input range,” IEEE Journal of Solid­State Cir cuits, vol. 19, no. 6, pp. 919–925, 1984.
[13] R. Reay and G. Kovacs, “An unconditionally stable two­stage CMOS amplifier,” IEEE Journal of Solid­State Circuits, vol. 30, no. 5, pp. 591–594, 1995.
[14] U. Dasgupta and Y. P. Xu, “Effects of resistive loading on unity gain frequency of two­stage CMOS operational amplifiers,” in 2003 IEEE International Symposium on Circuits and Systems (ISCAS), vol. 1, pp. I–I, 2003.
[15] P. Hurst, S. Lewis, J. Keane, F. Aram, and K. Dyer, “Miller compensation using current buffers in fully differential CMOS two­stage operational amplifiers,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 51, no. 2, pp. 275–285, 2004.
[16] M. Yavari, O. Shoaei, and F. Svelto, “Hybrid cascode compensation for two­stage CMOS operational amplifiers,” in 2005 IEEE International Symposium on Circuits and Systems, pp. 1565–1568 Vol. 2, 2005.
[17] H. Aminzadeh, R. Lotfi, and S. Rahimian, “Design Guidelines for Two­Stage Cascode­Compensated Operational Amplifiers,” in 2006 13th IEEE International Conference on Electronics, Circuits and Systems, pp. 264–267, 2006.
[18] V. Saxena and R. Baker, “Indirect feedback compensation of CMOS op­amps,” in 2006 IEEE Workshop on Microelectronics and Electron Devices, 2006. WMED ’06., pp. 2 pp.–4, 2006.
[19] V. Saxena and R. J. Baker, “Compensation of CMOS op­amps using split­length transistors,” in 2008 51st Midwest Symposium on Circuits and Systems, pp. 109– 112, 2008.
[20] U. Dasgupta, “Issues in “Ahuja"frequency compensation technique,” in 2009 IEEE International Symposium on Radio­Frequency Integration Technology (RFIT), pp. 326–329, 2009.
[21] V. Kursun, S. Narendra, V. De, and E. Friedman, “Low­voltage­swing monolithic dc­dc conversion,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 51, no. 5, pp. 241–248, 2004.
[22] Y. Jang, M. M. Jovanovic, and D. L. Dillman, “Light­Load Efficiency Optimization Method,” in 2009 Twenty­Fourth Annual IEEE Applied Power Electronics Confer ence and Exposition, pp. 1138–1144, 2009.
[23] S.­U. Shin, “An Analysis of Non­Isolated DC­DC Converter Topologies with Energy Transfer Media,” Energies, vol. 12, no. 8, 2019.
[24] J.­D. Suh, Y.­H. Yun, and B.­S. Kong, “High­Efficiency DC–DC Converter with Charge­Recycling Gate­Voltage Swing Control,” Energies, vol. 12, no. 5, 2019.
[25] M. Belloni, E. Bonizzoni, E. Kiseliovas, P. Malcovati, F. Maloberti, T. Peltola, and T. Teppo, “A 4­Output Single­Inductor DC­DC Buck Converter with Self­Boosted Switch Drivers and 1.2A Total Output Current,” in 2008 IEEE International Solid State Circuits Conference ­ Digest of Technical Papers, pp. 444–626, 2008.
[26] K. Ozanoglu and G. Dundar, “Single­Inductor Dual­Output Buck Converter with Charge Recycling,” in SMACD / PRIME 2021; International Conference on SMACD and 16th Conference on PRIME, pp. 1–4, 2021.
[27] C.­W. Chang and C.­L. Wei, “Single­inductor four­switch non­inverting buck­boost dc­dc converter,” in Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, pp. 1–4, 2011.
[28] A. Mishra, W. Zhu, B. Wicht, and V. D. Smedt, “An All­1.8­V­Switch Hybrid Buck– Boost Converter for Li­Battery­Operated PMICs Achieving 95.63 % Peak Efficiency Using a 288­m DCR Inductor,” IEEE Transactions on Power Electronics, vol. 38, no. 3, pp. 3444–3454, 2023.
[29] D. Kilani, B. Mohammad, H. Saleh, and M. Ismail, “LDO regulator versus switched inductor DC­DC converter,” in 2014 21st IEEE International Conference on Elec tronics, Circuits and Systems (ICECS), pp. 638–641, 2014.
[30] M. D. Seeman and S. R. Sanders, “Analysis and Optimization of Switched­Capacitor DC–DC Converters,” IEEE Transactions on Power Electronics, vol. 23, no. 2, pp. 841–851, 2008.
[31] J. Yao, K. Zheng, and A. Abramovitz, “Dynamic Analysis of the Switched Inductor Buck Converter,” in IECON 2019 ­ 45th Annual Conference of the IEEE Industrial Electronics Society, vol. 1, pp. 1721–1725, 2019.
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dc.identifier.urihttp://tdr.lib.ntu.edu.tw/jspui/handle/123456789/93221-
dc.description.abstract首先,本論文在第 1 章中提及目前降壓轉換器在設計上會遇到的困境。與通常用於推動輕負載的低壓差穩壓器相比,功率管理集成電路通常用於推動重負載,這意味著降壓轉換器的效率會因為導通損耗而嚴重降低。
本論文在第 2 章提出了一種全新的雙路徑降壓轉換器的功率級架構。與傳統降壓轉換器的功率級不同,本論文所提出的雙路徑降壓轉換器的功率級不僅可以通過更低的電感電流和更小體積的電感器來消除效率與功率密度之間的耦合,還可以通過預充電功率級的飛電容器,實現更高的電壓降比,從而在相同電壓降比下減少直流電壓轉換器的數量。
本論文會在第 3 章提及全新的雙路徑降壓轉換器的定性和定量分析,而第 4章將專注於模擬,第 5 章則將專注於測量。在這些章節中,全新的雙路徑降壓轉換器將會被拿來與傳統的降壓轉換器進行比較,比照在比較表 5.1 中提到的其他文獻 [1] [2] [3] [4] [5] 。該功率級在使用“0.18 微米 CMOS"製程的情況下,會在固定負載電流為 1 A 時達到 90.3 % 的峰值效率,而在固定轉換比為 0.27 時達到91.3 % 的峰值效率。
本論文將在第 6 章總結所提出的雙路徑降壓轉換器的研究成果,並提供未來的研究方向。
最後,附錄討論了各種類型的降壓轉換器,例如開關電容和開關電感降壓轉換器。還比較了開關電容、開關電感和混合降壓轉換器(雙路徑降壓轉換器)的優缺點。
zh_TW
dc.description.abstractFirst of all, the design challenges of buck converters would be mentioned in chapter 1. Especially being compared to an low­dropout regulator is usually adopted in a light load situation, a power management integrated circuit is usually adopted in a heavy load situation, which means the efficiency of a buck converter would be seriously degraded due to conduction power loss.
Then, a brand new structure of power stage for a dual path buck converter is proposed in chapter 2. Being compared to the power stage of conventional buck converter, the proposed power stage for a dual path buck converter not only can decouple the trade­off between efficiency and power density with lower current and smaller volume of inductor, but also achieve a higher voltage step­down ratio (cost less DC­DC converters than the others under the same voltage step­down ratio) by pre­charging flying capacitors of power stage.
As for analysis, simulation and measurement, both of qualitative and quantitative analysis would be proposed in chapter 3, and simulation would be proposed in chapter 4, and measurement would be proposed in chapter 5. In the chapters mentioned above, the proposed dual path buck converter would be compared to the conventional buck converter, just like the other paper [1] [2] [3] [4] [5] mentioned in comparision table 5.1. The power stage has the peak efficiency 90.3 % at fixed load current equals to 1 A, and peak efficiency 91.3 % at fixed conversion ratio equals to 0.27 under the process ”0.18 um CMOS”.
And the research of the proposed buck converter and further research directions would be summarized in chapter 6.
Last but not least, many other types of buck converters such as switched­capacitor and switched­inductor buck converter are mentioned in Appendix. We can tell the pros and cons of switched­capacitor, switched­inductor, and hybrid buck converter (dual path buck converter, DPBC as well) [6] [7] [8] [9] in this section.
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dc.description.provenanceSubmitted by admin ntu (admin@lib.ntu.edu.tw) on 2024-07-23T16:21:51Z
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dc.description.tableofcontentsAcknowledgements ii
摘要 iii
Abstract v
Contents vii
List of Figures xi
List of Tables xiii
Chapter 1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Thesis Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Chapter 2 Proposed Buck Converter 3
2.1 The Overall Structure . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2.1 Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2.2 On­Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2.3 Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2.4 Off Chip Inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2.5 Off Chip Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2.5.1 Off Chip Flying Capacitor . . . . . . . . . . . . . . . . 8
2.2.5.2 Off Chip Output Capacitor . . . . . . . . . . . . . . . 10
2.2.6 Off Chip Output Resistor . . . . . . . . . . . . . . . . . . . . . . . 11
2.3 Pulse­width Modulation Generator . . . . . . . . . . . . . . . . . . . 11
2.3.1 Ramp Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3.2 Compensator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3.3 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3.4 Non­overlap Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.5 Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Chapter 3 Analysis 15
3.1 Two Phase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2 Small Ripple Approximation . . . . . . . . . . . . . . . . . . . . . . 16
3.2.1 Conversion Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2.2 Inductor DC Current Ratio . . . . . . . . . . . . . . . . . . . . . . 19
3.2.3 Inductor Current Ripple Ratio . . . . . . . . . . . . . . . . . . . . 20
3.3 Small Signal Analysis . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.3.1 State Average . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.4 Power Loss of a Switch . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.4.1 Switching Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.4.2 Conduction Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.4.3 Dead Time Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.4.4 Gate Drive Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.4.5 Reverse Recovery Loss . . . . . . . . . . . . . . . . . . . . . . . . 27
3.4.6 Switching Capacitor Loss . . . . . . . . . . . . . . . . . . . . . . . 27
3.5 Power Loss of a Capacitor and an Inductor . . . . . . . . . . . . . . 27
3.5.1 Conduction Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.5.2 Core Loss of an Inductor . . . . . . . . . . . . . . . . . . . . . . . 29
3.6 Power Loss of the Proposed Dual Path Buck Converter . . . . . . . . 29
3.6.1 Conduction Loss Ratio With DC Resistance . . . . . . . . . . . . . 29
3.6.2 Conduction Loss With DC Resistance . . . . . . . . . . . . . . . . 30
Chapter 4 Simulation 32
4.1 Conventional Buck Converter . . . . . . . . . . . . . . . . . . . . . 33
4.2 The Proposed Dual Path Buck Converter . . . . . . . . . . . . . . . 34
Chapter 5 Measurement 35
5.1 Wire Bonding and Packaging . . . . . . . . . . . . . . . . . . . . . 35
5.2 Printed Circuit Board & Breadboard . . . . . . . . . . . . . . . . . . 36
5.3 Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.4 Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.5 Comparision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Chapter 6 Summary 42
6.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
References 44
Appendix A — Background Knowledge 49
A.1 Vehicle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
A.2 Li­Ion Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
A.3 C­Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
A.4 Converter Topology . . . . . . . . . . . . . . . . . . . . . . . . . . 50
A.4.1 Low­Dropout Linear Regulator . . . . . . . . . . . . . . . . . . . . 51
A.4.2 Switched­Capacitor Buck Converter . . . . . . . . . . . . . . . . . 51
A.4.3 Switched­Inductor Buck Converter . . . . . . . . . . . . . . . . . . 51
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dc.language.isoen-
dc.subject電源管理積體電路zh_TW
dc.subject效率zh_TW
dc.subject功率密度zh_TW
dc.subjectefficiencyen
dc.subjectpower management integrated circuiten
dc.subjectPMICen
dc.subjectpower densityen
dc.title具高功率密度功率級之雙路徑降壓轉換器zh_TW
dc.titleA Dual Path Buck Converter With A High Power Density Power Stageen
dc.typeThesis-
dc.date.schoolyear112-2-
dc.description.degree碩士-
dc.contributor.oralexamcommittee鄭士康;張勝良zh_TW
dc.contributor.oralexamcommitteeShyh-Kang Jeng;Sheng-Lyang Jangen
dc.subject.keyword電源管理積體電路,效率,功率密度,zh_TW
dc.subject.keywordpower management integrated circuit,efficiency,power density,PMIC,en
dc.relation.page51-
dc.identifier.doi10.6342/NTU202401472-
dc.rights.note未授權-
dc.date.accepted2024-07-12-
dc.contributor.author-college電機資訊學院-
dc.contributor.author-dept電子工程學研究所-
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