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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 胡振國 | zh_TW |
| dc.contributor.advisor | Jenn-Gwo Hwu | en |
| dc.contributor.author | 龔泰銘 | zh_TW |
| dc.contributor.author | Tai-Ming Kung | en |
| dc.date.accessioned | 2024-07-12T16:20:40Z | - |
| dc.date.available | 2024-07-13 | - |
| dc.date.copyright | 2024-07-12 | - |
| dc.date.issued | 2024 | - |
| dc.date.submitted | 2024-07-09 | - |
| dc.identifier.citation | [1] C. Wann, K. Noda, T. Tanaka, M. Yoshida, and C. Hu, “A comparative study of advanced mosfet concepts,” IEEE Transactions on Electron Devices, vol. 43, no. 10, pp. 1742–1753, 1996.
[2] T. Sakurai and A. Newton, “A simple mosfet model for circuit analysis,” IEEE Transactions on Electron Devices, vol. 38, no. 4, pp. 887–894, 1991. [3] Y. Cheng, M. Deen, and C.-H. Chen, “Mosfet modeling for rfic design,” IEEE Transactions on Electron Devices, vol. 52, no. 7, pp. 1286–1303, 2005. [4] J. McCreary, “Matching properties, and voltage and temperature dependence of mos capacitors,” IEEE Journal of Solid-State Circuits, vol. 16, no. 6, pp. 608–616, 1981. [5] J.-B. Shyu, G. Temes, and F. Krummenacher, “Random error effects in matched mos capacitors and current sources,” IEEE Journal of Solid State Circuits, vol. 19, no. 6, pp. 948–956, 1984. [6] N. S. Saks, M. G. Ancona, and J. A. Modolo, “Radiation effects in mos capacitors with very thin oxides at 80°k,” IEEE Transactions on Nuclear Science, vol. 31, no. 6, pp. 1249–1255, 1984. [7] E. J. Charlson and J. C. Lien, “An Al p-silicon MOS photovoltaic cell,” Journal of Applied Physics, vol. 46, no. 9, pp. 3982–3987, 09 1975. [8] S. Sadhukhan, S. Acharya, T. Panda, N. C. Mandal, S. Bose, A. Nandi, G. Das, S. Chakraborty, S. Maity, P. Chaudhuri, and H. Saha, “Detailed Study on the Role of Nature and Distribution of Pinholes and Oxide Layer on the Performance of Tunnel Oxide Passivated Contact (TOP Con) Solar Cell,” IEEE Trans. Electron Devices, vol. 69, no. 10, pp. 5618–5623, 2022. [9] T.-Y. Chen and J.-G. Hwu, “Two states phenomenon in the current behavior of metal-oxide-semiconductor capacitor structure with ultrathin SiO2,” Appl. Phys. Lett., vol. 101, no. 7, p. 073506, 08 2012. [10] S.-W. Huang and J.-G. Hwu, “Improved Two States Characteristics in MIS Tunnel Diodes by Oxide Local Thinning Enhanced Transient Current Behavior,” IEEE Trans. Electron Devices, vol. 69, no. 12, pp. 7107–7112, 2022. [11] C.-S. Liao and J.-G. Hwu, “Remote Gate-Controlled Negative Transconductance in Gated MIS Tunnel Diode,” IEEE Trans. Electron Devices, vol. 63, no. 7, pp. 2864–2870, 2016. [12] W.-C. Kao, J.-Y. Chen, and J.-G. Hwu, “Two States Phenomenon Induced By Neighboring Device Coupling Effect in MIS(p) Tunnel Current,” ECS Trans., vol. 72, no. 2, p. 223, apr 2016. [13] J.-H. Chen, K.-C. Chen, and J.-G. Hwu, “Fringing field induced current coupling in concentric metal–insulator–semiconductor (MIS) tunnel diodes with ultra-thin oxide,” AIP Adv., vol. 12, no. 4, p. 045116, 04 2022. [14] P. Magnan, “Detection of visible photons in ccd and cmos: A comparative view,” Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, vol. 504, no. 1, pp. 199–212, 2003, proceedings of the 3rd International Conference on New Developments in Photodetection. [15] G. E. Smith, “Nobel lecture: The invention and early history of the ccd,” Rev. Mod. Phys., vol. 82, pp. 2307–2312, Aug 2010. [16] H. Faraji and W. MacLean, “Ccd noise removal in digital images,” IEEE Transactions on Image Processing, vol. 15, no. 9, pp. 2676–2685, 2006. [17] J. H. Chen, K. C. Chen, and J. G. Hwu, “Energy-Saving Logic Gates Utilizing Coupling Phenomenon Between MIS(p) Tunneling Diodes,” IEEE Trans. Electron Devices, vol. 68, no. 12, pp. 6558–6562, 2021. [18] M. Tanaka and S. Sugahara, “Mos-based spin devices for reconfigurable logic,” IEEE Transactions on Electron Devices, vol. 54, no. 5, pp. 961 976, 2007. [19] Q. Xie, S. Deng, M. Schaekers, D. Lin, M. Caymax, A. Delabie, X.-P. Qu, Y.-L. Jiang, D. Deduytsche, and C. Detavernier, “Germanium surface passivation and atomic layer deposition of high-k dielectrics—a tutorial review on ge-based mos capacitors,” Semiconductor Science and Technology, vol. 27, no. 7, p. 074012, jun 2012. [20] P. Tirmali, A. G. Khairnar, B. N. Joshi, and A. Mahajan, “Structural and electrical characteristics of rf-sputtered hfo2 high-k based mos capacitors,” Solid-State Electronics, vol. 62, no. 1, pp. 44–47, 2011. [21] P. Xia, X. Feng, R. J. Ng, S. Wang, D. Chi, C. Li, Z. He, X. Liu, and K.-W. Ang, “Impact and origin of interface states in mos capacitor with monolayer mos2 and hfo2 high-k dielectric,” Scientific reports, vol. 7, no. 1, p. 40669, 2017. [22] H. Liu, A. T. Neal, and P. D. Ye, “Channel length scaling of mos2 mosfets,” ACS nano, vol. 6, no. 10, pp. 8563–8569, 2012. [23] A. Sengupta, A. Chanana, and S. Mahapatra, “Phonon scattering limited performance of monolayer MoS2 and WSe2 n-MOSFET,” AIP Advances, vol. 5, no. 2, p. 027101, 02 2015. [24] C.-S. Liao, W.-C. Kao, and J.-G. Hwu, “Energy-saving write/read operation of memory cell by using separated storage device and remote reading with an mis tunnel diode sensor,” IEEE Journal of the Electron Devices Society, vol. 4, no. 6, pp. 424–429, 2016. [25] Y.-K. Lin and J.-G. Hwu, “Photosensing by edge schottky barrier height modulation induced by lateral diffusion current in mos (p) photodiode,” MANUSCRIPT 7 IEEE Transactions on Electron Devices, vol. 61, no. 9, pp. 3217–3222, 2014. [26] C.-F. Yang and J.-G. Hwu, “Role of fringing field on the electrical characteristics of metal-oxide-semiconductor capacitors with co-planar and edge-removed oxides,” AIP Advances, vol. 6, no. 12, 2016. [27] G. Jain, A. Prasad, and B. Chakravarty, “On the Mechanism of the Anodic Oxidation of Si at Constant Voltage,” J. Electrochem. Soc., vol. 126, no. 1, p. 89, Jan. 1979. [28] P. Schmidt and W. Michel, “Anodic formation of oxide films on silicon,” Journal of the electrochemical society, vol. 104, no. 4, p. 230, 1957. [29] S. K. Ghandhi, VLSI fabrication principles: silicon and gallium arsenide. John Wiley & Sons, 1994. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/93027 | - |
| dc.description.abstract | 本篇論文主旨在於討論相鄰之同心圓環金氧半穿隧二極體結構之電流電壓特性及其電流之耦合現象，並利用此耦合特性提出一種可能的邏輯閘應用。在第二章節中，我們觀察了在擁有完整外環的同心圓環元件中，外環與中心圓元件之電流電壓特性。並且使用了兩種不同的結構包括，共平面氧化層元件及閘極外圍氧化層移除之元件來進行對比。發現在掃動外環電壓之同時將中心圓偏壓固定，發現中心圓電流會呈現不同的極性變化。本研究對於此種特性提出了關於此兩種不同結構之耦合效應之解釋，並針對閘極外圍氧化層移除之元件，提出可能之邏輯閘應用。在第三章節中，同樣在兩種架構下將外環分割成三個相同大小之扇形，並觀察不同數量之外環輸入對於中心圓電流特性之影響。為了印證所提出的物理模型，在此章節中同時使用了Silvaco TCAD來進行分析。並且提出了基於共平面氧化層元件結構之邏輯應用。最後在第四章節中提出了未來可行的研究方向建議。 | zh_TW |
| dc.description.abstract | This thesis focuses on the discussion of the current-voltage characteristics and current coupling phenomena of adjacent concentric metal-insulator-semiconductor tunnel diodes (MISTDs) structures. Utilizing these coupling properties, some possible applications of logic gates based on these MISTDs are proposed. In chapter 2, we observed the current-voltage characteristics between the outer ring and the inner center in MISTD devices with complete outer ring. Two different structures, namely planar (PL) and edge-removed (ER) devices, were compared. It was found that while sweeping the outer ring voltage with a fixed center bias, the polarity of the center current varied. An explanation of this characteristic regarding the coupling effects of these two different structures was provided. Additionally, a potential logic gate application based on ER devices was proposed. In chapter 3, under the same two structures, the outer ring was divided into three equal-sized sectors, and the influence of different numbers of outer ring inputs on the center current characteristics was observed. To validate the proposed physical models, Silvaco TCAD was used for verification in this chapter. A logic application based on coplanar oxide-layer devices was also proposed. Finally, in chapter 4, potential future research directions were suggested. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2024-07-12T16:20:40Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2024-07-12T16:20:40Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 致謝... I
摘要... II Abstract... III Contents... IV Table Captions... VI Figure Captions... VII Chapter 1 Introduction... 1 1-1 Motivation and Thesis Organization... 2 1-2 I-V Characteristic of MIS(p) Tunnel Diodes... 4 1-2-1 Oxide Thickness Effect on MISTD... 4 1-2-2 Planar and Edge-Removed Oxides Devices... 5 1-2-3 Voltage Coupling of Multi-Rings MISTD Structure... 6 1-3 TCAD Simulation... 7 1-4 Growth Mechanism of Constant Voltage Anodization of Silicon... 7 1-5 Summary... 9 Chapter 2 Current Coupling Effect in Planar and Edge-Removed Couple MISTDs... 15 2-1 Introduction... 16 2-2 Experimental and TCAD Simulation... 16 2-3 Results and Discussion... 17 2-3-1 Coupling Current-Voltage Characteristics of Couple MISTDs... 17 2-3-2 Current-Voltage Characteristics with Various Oxide Gaps and Thickness... 19 2-3-3 Physical Mechanism of Center Current Reversal Phenomenon... 20 2-3-4 Logic Gates Applications... 22 2-4 Summary... 23 Chapter 3 Current Coupling Effect of Multi-Rings Couple MISTDs... 39 3-1 Introduction... 40 3-2 Experimental and TCAD Simulation... 40 3-3 Results and Discussion... 41 3-3-1 Current-Voltage Characteristics of Multi-Rings Couple MISTDs... 41 3-3-2 Physical Mechanism of Current-Voltage Characteristics... 43 3-3-3 TCAD Simulation Results... 46 3-3-4 Logic Gates Applications... 48 3-4 Summary... 50 Chapter 4 Conclusion and Future Work... 65 4-1 Conclusion... 66 4-2 Suggestion for Future Work... 67 4-2-1 The Coupling Current-Voltage Characteristics of ER Couple MISTDs... 67 4-2-2 Extension of Multi-Rings Couple MISTDs Logic Application... 68 References... 70 | - |
| dc.language.iso | en | - |
| dc.subject | 金氧半穿隧二極體 | zh_TW |
| dc.subject | 閘極外圍氧化層移除 | zh_TW |
| dc.subject | 耦合效應 | zh_TW |
| dc.subject | 多階態電流 | zh_TW |
| dc.subject | 邏輯閘 | zh_TW |
| dc.subject | 低功耗 | zh_TW |
| dc.subject | coupling effect | en |
| dc.subject | Metal-insulator-semiconductor tunnel diode (MISTD) | en |
| dc.subject | low power | en |
| dc.subject | logic gates | en |
| dc.subject | multilevel current | en |
| dc.subject | edge-removed (ER) | en |
| dc.title | 鄰近同心金氧半穿隧二極體之電流耦合效應及邏輯閘應用 | zh_TW |
| dc.title | Current Coupling Effect in Adjacent Concentric Metal-Insulator-Semiconductor Tunnel Diodes and Its Application of Logic Gates | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 112-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 吳肇欣;吳幼麟 | zh_TW |
| dc.contributor.oralexamcommittee | Chao-Hsin Wu;You-Lin Wu | en |
| dc.subject.keyword | 金氧半穿隧二極體,閘極外圍氧化層移除,耦合效應,多階態電流,邏輯閘,低功耗, | zh_TW |
| dc.subject.keyword | Metal-insulator-semiconductor tunnel diode (MISTD),edge-removed (ER),coupling effect,multilevel current,logic gates,low power, | en |
| dc.relation.page | 74 | - |
| dc.identifier.doi | 10.6342/NTU202401608 | - |
| dc.rights.note | 未授權 | - |
| dc.date.accepted | 2024-07-09 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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