低功率有線傳輸接收機設計

Abstract

大數據時代，各種數據交換及資料傳遞的有線傳輸應用與需求大幅提高，進而相繼發展出高速、多路傳輸的有線傳輸技術。基於擴展有線通訊系統頻寬的強勁趨勢，高性能的收發器於功率消耗上勢必大幅提升，然而提供的能量總量必然是有限額度，因此高性能與高效能需要同時滿足。為了因應這些趨勢與挑戰，本文首先提出了基於有線傳輸的能量獵取技術，採用三相位旋轉及五倍時間相交之切換式電容電路嵌入於通訊電路前端介面，藉由切換式電容模仿50 歐姆，滿足訊號完整度，同時獵取有線傳輸的訊號能量達300微瓦，此提出的獵能電路採用台積電四零奈米製程。接著，本論文分析現有文獻，歸納出有線傳輸的時脈分配電路於功率消耗上有高度佔比，在提出的接收機中，採用次鮑時脈架構達到降低電路功耗，並搭載連續時間線性等化器、一階決策回授等化器，以及時脈資料回復電路，達到高性能、高效能之有線傳輸接收機，此提出的有線傳輸接收機採用台積電二八奈米製程，總功率為18 毫瓦。 總體而言，此論文強調了現代有線通訊系統中的功率效率挑戰，並提出了可行的技術解決方案，在保持高性能標準的同時優化能耗，從而促進更可持續和更高效的有線通信技術。

In the era of big data, the demand for advanced wireline transmission technologies has surged, driven by the need for high-speed and multichannel data exchange and transfer. These developments have necessitated enhancements in wireline communication bandwidth, significantly increasing high-performance transceivers’ power consumption. Given the limited availability of energy resources, achieving a balance between high performance and high efficiency is imperative. This thesis introduces an innovative energy harvesting technique for wireline transmissions to address these trends and challenges. This technique utilizes a switched capacitor circuit that features three-phase rotation and five-time interleaving, which is embedded into the I/O interface of the communication circuit. By mimicking a 50ohm termination using the switched capacitor, this approach maintains signal integrity and enables the harvesting of up to 300 microwatts of energy from the wireline transmission. This energy harvesting circuit is implemented using TSMC 40nm CMOS technology.

Additionally, a review of the existing literature reveals that the clock distribution circuit in wireline transmissions is a major contributor to power consumption. To address this, the proposed receiver incorporates a sub-baud-rate clock architecture to minimize power usage. The receiver also features a continuous-time linear equalizer, a 1tap decision feedback equalizer, and a clock and data recovery circuit, which collectively enhance the performance and efficiency of wired transmission. This proposed receiver fabricated in a TSMC 28nm CMOS technology consumes 18 mW.

This thesis highlights the power efficiency challenges in modern wireline communication systems. It proposes viable technological solutions that optimize energy consumption while maintaining high-performance standards, thus facilitating more sustainable and efficient wireline communication technologies.