基於超尺度二維材料的先進電子元件

Abstract

本論文包括兩個主要目標。第一部分的目標為推動奈米尺度下的二維材料裝置的製成過程、材料選擇、以及表徵分析，並且突破光刻顯影的限制。二維材料被認為是高縮放裝置中矽電晶體通道的有前途的繼承者，促使對於要了解它們在奈米尺度下的行為的廣泛研究。目前的研究被侷限於直接圖案化的方法，進而限制其解析度以及引入缺陷。本論文呈現一個自膨脹多重圖案化過程，展現其能夠以低複雜度大規模的製造出具有前所未有的精密度的二維材料特徵的淺力。該過程結合了心軸的光刻顯影以及自下而上的自膨脹，得到低了光刻顯影極限一個數量級的解析度。自膨脹雙圖案化（SEDP）過程的深入表徵分析揭露了透過自我限制和溫度控制的氧化過程對臨界尺寸進行奈米級的精準控制。結果證實 SEDP 過程可以保留二維材料的品質和型態，這一點已得到高解析度顯微鏡和光譜學的證實。此創新方法為研究用於未來電子裝置的高性能、超大規模二維材料元件開闢了新途徑。第二部分探討了為基於二維材料的晶體通道形成高性能閘所面臨的挑戰，其困難來自於要沉積具有足夠質量以及可控厚度的電介質。本論文通過展示凡德瓦整合的一個獨立的 Al2O3 介電膜提出了一種解決方案，將其作為一種簡單、可擴展且功能強大的閘介電層。我們開發了一種用於非結晶特氧化鋁層的濕轉移法，其等效氧化物厚度（EOT）在單納米範圍內可做微調。電學表徵分析證實了電介質的高崩潰電場和低漏電性質。與二維材料電晶體的整合顯示了高性能。電介膜的晶圓大小均勻性使其能大規模的成為具有良好穩健性和長期穩定度的柔性裝置。這項研究顯著地有助於解決基於二維材料的電子元件所面臨的挑戰並為了提高元件性能和靈活性提供了實用的解決方案。

The dissertation comprises two primary objectives. In the first part, the goal is to advance the fabrication process, material selection, and characterization of nanoscale devices made from 2D materials, surpassing the limitations of lithography. 2D materials are considered as promising alternatives to silicon channel transistors in ultimately scaled devices, significant research efforts are needed to understand their behavior at the nanoscale. Current research has been constrained by direct patterning approaches, limiting resolution and introducing defects. The dissertation presents a self-expansion-based multi-patterning approach, showcasing its potential for the fabrication of 2D material features with low complexity and unprecedented precision at a large scale. The method involves combining lithographical patterning of a mandrel with bottom-up self-expansion process, achieving pattern resolution one order of the magnitude below the lithographic limits. In-depth characterization of the self-expansion double patterning (SEDP) process reveals nanometer-precision manipulation of critical dimensions through a self-aligned and temperature-controlled surface oxidation process. Results demonstrates that the SEDP process can restore the morphology and quality of 2D materials, as confirmed by optical spectroscopy and high-resolution microscopy. This innovative approach opens new routes for research in high-performance, ultra-scaled 2D material devices based next generation future electronics. The second part of the dissertation addresses the challenge of forming a high-performance gate terminal for 2D materials-based transistors, given difficulties in depositing a dielectric with sufficient quality and controllable thickness. The dissertation proposes a solution by demonstrating the van-der-Waals integration of a free-standing Al2O3 dielectric membrane, presenting it as a facile, scalable, and powerful gate dielectric. A process is developed for the wet transfer of an amorphous alumina layer with a finely adjustable equivalent oxide thickness (EOT) in the single nanometer range. Electrical characterization confirms the high breakdown field and low leakage of the dielectric. Integration into 2D materials transistors reveals high performance. The wafer-scale uniformity of the dielectric membrane allows the formation of large-scale flexible devices with good robustness and long-term stability. This research significantly contributes to addressing challenges in 2D materials-based electronics and offers practical solutions for enhancing device performance and flexibility