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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳景然 | zh_TW |
dc.contributor.advisor | Ching-Jan Chen | en |
dc.contributor.author | 李國維 | zh_TW |
dc.contributor.author | Guo-Wei Li | en |
dc.date.accessioned | 2024-05-14T16:07:52Z | - |
dc.date.available | 2024-05-15 | - |
dc.date.copyright | 2024-05-14 | - |
dc.date.issued | 2024 | - |
dc.date.submitted | 2024-05-07 | - |
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Lima, "Level Shifters and DCVSL for a Low-Voltage CMOS 4.2-V Buck Converter," in IEEE Transactions on Industrial Electronics, vol. 55, no. 9, pp. 3315-3323, Sept. 2008, doi: 10.1109/TIE.2008.927974. [15] Y. Yan, P. -H. Liu, F. Lee, Q. Li and S. Tian, "V2 control with capacitor current ramp compensation using lossless capacitor current sensing," 2013 IEEE Energy Conversion Congress and Exposition, Denver, CO, USA, 2013, pp. 117-124, doi: 10.1109/ECCE.2013.6646689. [16] S. Pennisi, "High accuracy CMOS capacitance multiplier," 9th International Conference on Electronics, Circuits and Systems, Dubrovnik, Croatia, 2002, pp. 389-392 vol.1, doi: 10.1109/ICECS.2002.1045415. [17] T. B. Nazzal and S. A. Mahmoud, "Low-power bootstrapped sample and hold circuit for analog-to-digital converters," 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS), Abu Dhabi, United Arab Emirates, 2016, pp. 1-4, doi: 10.1109/MWSCAS.2016.7870027. [18] Weize Xu and E. G. Friedman, "Clock feedthrough in CMOS analog transmission gate switches," 15th Annual IEEE International ASIC/SOC Conference, Rochester, NY, USA, 2002, pp. 181-185, doi: 10.1109/ASIC.2002.1158052. [19] H. Wang, Z. Qiao, Y. Xu and G. Zhang, "Design Procedure for a Folded-Cascode and Class AB Two-Stage CMOS Operational Amplifier," 2019 IEEE International Conference of Intelligent Applied Systems on Engineering (ICIASE), Fuzhou, China, 2019, pp. 40-43, doi: 10.1109/ICIASE45644.2019.9074153. [20] P. Kumar et al., "A 0.4V∼1V 0.2A/mm2 70% efficient 500MHz fully integrated digitally controlled 3-level buck voltage regulator with on-die high density MIM capacitor in 22nm tri-gate CMOS," 2015 IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, USA, 2015, pp. 1-4, doi: 10.1109/CICC.2015.7338479. [21] J. Xue and H. Lee, "A 2 MHz 12–100 V 90% Efficiency Self-Balancing ZVS Reconfigurable Three-Level DC-DC Regulator With Constant-Frequency Adaptive-On-Time V2V^{2} Control and Nanosecond-Scale ZVS Turn-On Delay," in IEEE Journal of Solid-State Circuits, vol. 51, no. 12, pp. 2854-2866, Dec. 2016, doi: 10.1109/JSSC.2016.2606581. | - |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/92625 | - |
dc.description.abstract | 在論文中提出了一種具有電容器電流逆電荷固定導通時間(iCAPQCOT)控制的三階降壓轉換器積體電路(IC)。電容器電流逆電荷固定導通時間控制在占空比為0.5時避免了不穩定性問題,並增強了負載瞬態響應。該控制將補償電壓和電感電流產生的積分電壓與感知到的電容電流進行比較。積分電壓在占空比為0.5時具有適當的斜率,此時電感電流漣波為0。感知到的電容電流顯示了負載電流變化,並增強了負載瞬態響應。此外,提出了全範圍轉換點電壓偵測飛馳電容電壓平衡控制(Full-Range V_LX Sensing Flying Capacitor Voltage Balance Control)。通過偵測,可以在連續和間斷導通模式以及整個占空比範圍內平衡電容器電壓,而先前的技術無法實現。轉換器積體電路採用了TSMC的180nm CMOS工藝,使用了1.8V純NMOS電晶體功率級。模擬結果表明,在連續導通模式下,開關頻率達到2 MHz,在佔空比小於0.5時可以隨負載調節開關頻率。峰值效率為97.2%。當負載瞬態從10 mA變化到1.5 A時,所提出的控制實現了25 mV的輸出電壓下衝。與逆電荷固定導通時間控制(IQCOT)相比,負載切換時輸出電壓的下衝減少了77%。此外,全範圍轉換點電壓偵測飛馳電容電壓平衡控制只需要45 μS即可平衡電容電壓,比不使用飛馳電容電壓平衡要快近3倍。由於晶片功率級出現異常工作的問題,我們使用外部功率級替換了晶片上的功率級並連接到晶片上。測量結果表明,IQCOT控制即使在占空比為0.5時也可以穩定。 | zh_TW |
dc.description.abstract | A three-level buck converter integrated circuit (IC) with capacitor-current inverse-charge-COT (iCAPQCOT) control is proposed in the thesis. The iCAPQCOT control avoids instability issues when the duty cycle is 0.5 and enhances load transient response. This control strategy compares the integral voltage generated by the compensation voltage and inductor current with the sensed capacitor current. The integral voltage has a proper slope at 0.5 duty cycle where the inductor current ripple is canceled. The sensed capacitor current reveals load current change and enhances load transient response. Additionally, full-range V_LX sensing flying capacitor voltage balance control is proposed by detecting V_LX. The capacitor voltage can be balanced in both continuous and discontinuous conduction modes and throughout the entire duty cycle range, which is not achieved in prior arts. The converter IC was fabricated with a 1.8V pure NMOS transistor power stage using TSMC’s 180nm CMOS process. Simulation results show that the switching frequency reaches 2 MHz in continuous conduction mode, and can be scaled with the load when the duty cycle is less than 0.5. The peak efficiency is 97.2%. When the load transient changes from 10 mA to 1.5 A, the proposed control achieves 25 mV output voltage undershoot. Compared with Inverse Charge Constant On-Time Control (IQCOT), the output voltage undershoot under load switching is reduced by 77%. Besides, the full-range V_LX sensing flying capacitor voltage balance control only takes 45 μS to balance the capacitor voltage, which is nearly 3 times faster than without using flying capacitor voltage balance. Due to the issue of the chip’s power stage not operating normally, we used an external power stage to replace the on-chip power stage and connect it to the chip. The measurement results show that IQCOT control can stabilize even when the duty cycle is 0.5. | en |
dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2024-05-14T16:07:52Z No. of bitstreams: 0 | en |
dc.description.provenance | Made available in DSpace on 2024-05-14T16:07:52Z (GMT). No. of bitstreams: 0 | en |
dc.description.tableofcontents | 致謝 I
中文摘要 III Abstract IV Table of Contents VI List of Figures VIII List of Tables XV Chapter 1 Introduction 1 1.1 Background 1 1.2 Comparing Topologies: Three-Level vs. Conventional Buck Converters 1 1.3 Practical Challenges in Three-Level Buck Converters 7 1.4 Prior Works 7 1.5 Research Objectives and Chip Specifications 17 1.6 Thesis Outline 19 1.7 Contribution 20 Chapter 2 3L Buck Converter and Proposed Control Scheme 21 2.1 Proposed Capacitor-Current Inverse-Charge-COT (iCAPQCOT) Control 22 2.2 Full-Range VLX Sensing Capacitor Voltage Balance Control 29 2.3 Driver System and Mechanism 33 2.4 Noise Subtractor Architecture 39 2.5 Adaptive Constant On-Time 42 Chapter 3 Circuit Implementations 45 3.1 Corner and Temperature effect in TSMC 180nm 45 3.2 Power Stage 48 3.3 Noise Subtractor 51 3.4 Capacitor Sensor 53 3.5 Compensator Circuit 55 3.6 Modulation Circuit 59 3.7 TON Generator Circuit 66 3.8 Cap. Voltage Balance Circuit 70 3.9 Zero Current Detection (ZCD) Circuit 73 Chapter 4 Simulation Results 75 4.1 Efficiency and ILS Frequency 75 4.2 Load Transient Response 78 4.3 Line Transient Response 80 Chapter 5 Discrete Components Power Stage and Measurement Results 84 5.1 Discrete Components Power Stage 84 5.2 Measurement Results 93 Chapter 6 Conclusion and Future Works 103 6.1 Conclusion 103 6.2 Future Works 107 Reference 110 | - |
dc.language.iso | en | - |
dc.title | 電容電流反向電荷定導通時間控制之快速暫態響應三階降壓轉換器 | zh_TW |
dc.title | A Fast Transient Response Three-Level Buck Converter with Capacitor-Current Inverse-Charge-COT (iCAPQCOT) Control | en |
dc.type | Thesis | - |
dc.date.schoolyear | 112-2 | - |
dc.description.degree | 碩士 | - |
dc.contributor.oralexamcommittee | 林景源;陳耀銘 | zh_TW |
dc.contributor.oralexamcommittee | Jing-Yuan Lin;Yao-Ming Chen | en |
dc.subject.keyword | 三階降壓轉換器,低耐壓純NMOS電晶體功率級,逆電荷固定導通時間控制,電容器電流逆電荷固定導通時間控制,全範圍轉換點電壓偵測飛馳電容電壓平衡控制, | zh_TW |
dc.subject.keyword | three-level buck converter,Low-Voltage-Tolerant Pure NMOS Transistor Power Stage,Inverse Charge Constant On-Time Control,Capacitor-Current Inverse-Charge-COT,Full-Range V_LX Sensing Flying Capacitor Voltage Balance Control, | en |
dc.relation.page | 115 | - |
dc.identifier.doi | 10.6342/NTU202400938 | - |
dc.rights.note | 未授權 | - |
dc.date.accepted | 2024-05-07 | - |
dc.contributor.author-college | 電機資訊學院 | - |
dc.contributor.author-dept | 電子工程學研究所 | - |
顯示於系所單位: | 電子工程學研究所 |
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