請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/92622完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 林宗賢 | zh_TW |
| dc.contributor.advisor | Tsung-Hsien Lin | en |
| dc.contributor.author | 侯家蓉 | zh_TW |
| dc.contributor.author | Chia-Jung Hou | en |
| dc.date.accessioned | 2024-05-14T16:06:58Z | - |
| dc.date.available | 2024-05-15 | - |
| dc.date.copyright | 2024-05-14 | - |
| dc.date.issued | 2023 | - |
| dc.date.submitted | 2024-05-10 | - |
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/92622 | - |
| dc.description.abstract | 本論文提出應用於離子感測場效電晶體感測器之類比前端校正電路及讀取電路，此電路的主要任務為將場效電晶體的輸出訊號轉換為數位輸出，同時將過大的直流偏壓電流消除。
本篇一共實作了兩個電路。第一顆晶片為一兩位元類比前端直流電流抵銷系統及二階五位元之連續時間三角積分調變器，此晶片實作於台積電180奈米製程。利用前景校正的方式，抵銷系統消除不含感測資訊之直流訊號，確保後端不會因此飽和的同時降低其輸入範圍要求。在讀取電路的部分，直接以電流作為輸入訊號以減少額外元件造成的耗能，重複使用前端系統的積分器以節省面積，第二級積分器則使用較高面積效益的壓控震盪器來實現。晶片核心面積為0.4212平方毫米，整體功耗為127.09微瓦特，在11.9微安培輸入電流下達到75.9 dB的信號與雜訊比(頻寬為1 kHz)，在品質因素方面達到FoMs = 144.49 dB及FoMw = 14.01 pJ/conv。 第二顆晶片實作七位元類比前端直流電流抵銷系統及二階六位元之離散時間三角積分調變器，此晶片實作於台積電180奈米製程。讀取電路的部分，輸入訊號接收電壓、電流及溫度訊號，採用由一位元比較器及六位元連續漸進式類比數位轉換器組成的多量化器。以偽偽差動架構解決單端輸入系統不線性的問題。晶片核心面積為0.4051平方毫米，整體功耗為97.7微瓦特，在正負200毫伏特輸入電壓下達到74.02 dB的信號與雜訊比(頻寬為4 kHz)，在品質因素方面達到FoMs = 150.14 dB及FoMw = 2.97 pJ/conv。 | zh_TW |
| dc.description.abstract | This thesis proposes the analog front-end (AFE) calibration system and readout circuit for the Ion-Sensitive Field-Effect Transistors (ISFETs) sensor. The main task is to cancel out the DC bias current of the sensor while converting the input signals into digital outputs.
In this thesis, two circuits have been implemented. The first one realizes a 2-bit DC current cancellation system and an area-efficient voltage-controlled oscillator (VCO) based 2nd-order continues-time delta-sigma modulator (CTDSM). It is fabricated in a TSMC 180-nm process. The CTDSM takes a current input signal and reuses the integrator for the cancellation system to reduce power consumption. The core area of this chip is 0.4212 mm2 and the overall power consumption is 127.09 W. The SNR is 75.9 dB (with a bandwidth of 1 kHz) under 11.9 A input signal. The figure of merits (FoM) FoMs equals 144.86 dB and FoMw is 12.514 pJ/conv. The second one realizes a 7-bit cancellation system and 2nd-order discrete-time delta-sigma modulator (DTDSM) based on a dual-quantization architecture that employs a comparator and a 6-bit successive approximation register (SAR) analog-to-digital converter (ADC). The pseudo-pseudo differential (PPD) structure eliminates the non-linearity of single-ended structures. The core area of this chip is 0.388 mm2 and the overall power consumption is 97.7 W. The SNDR is 74.02 dB (with a bandwidth of 4 kHz) under ±200 mV input signal, achieving FoMs equal to 150.14 dB and FoMw is 2.97 pJ/conv. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2024-05-14T16:06:58Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2024-05-14T16:06:58Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 口試委員審定書 i
摘要 v Abstract vii List of Figures xii List of Tables xvi Chapter 1 Introduction 1 1.1 Background 1 1.2 Thesis Overview 2 Chapter 2 Fundamental of ISFET and Sensor Design 5 2.1 Working principle of ISFET 5 2.2 Sensor Nonidealities 7 2.2.1 Trapped Charge 7 2.2.2 Capacitive Attenuation 7 2.2.3 Drift 8 2.2.4 Temperature 9 2.3 General Sensor Design 10 2.3.1 ISFET Array for Ion Imaging 10 2.3.2 Capacitor Array for Touch Sensor 11 Chapter 3 Review of Delta Sigma Modulators 13 3.1 Introduction 13 3.2 Design variables of Delta Sigma Modulators 14 3.2.1 Quantizer 14 3.2.2 DAC 15 3.2.3 Loop Filter Architectures 16 3.2.4 Other Design Parameters 17 3.2.5 Difference between DT/CT DSM 17 3.3 Design Flow 19 3.3.1 DTDSM 19 3.3.2 DAC 21 3.3.3 From DTDSM to CTDSM 23 Chapter 4 Design of a 2nd-order Continuous-Time Delta-Sigma ADC with VCO-based Quantizer for ISFET Sensing 25 4.1 Introduction 25 4.2 System Architecture 29 4.2.1 DC Current Cancellation Loop 29 4.2.2 Loop Filter Architecture 30 4.2.3 Noise Analysis 31 4.3 Circuit Implementation 33 4.3.1 RC Integrator and Proportional-Integral Structure 33 4.3.2 VCO-based Integrator and Quantizer 35 4.3.3 Feedback IDAC 37 4.3.4 DC Current Cancellation Loop 38 4.4 Measured Results 40 4.4.1 Die photo 40 4.4.2 Measurement Environment Setup 40 4.4.3 Measured Results 42 4.5 Summary 46 Chapter 5 Design of a 2nd-order Discrete-Time Delta-Sigma ADC with Dual Quantizer for ISFET Sensing 47 5.1 Introduction 47 5.2 System Architecture 52 5.2.1 DC Cancellation Loop 55 5.2.2 Pseudo-Pseudo-Differential (PPD) 58 5.2.3 Loop Filter Architecture 63 5.2.4 Dual-Quantization-Based (Dual-QTZ) Modulator 66 5.2.5 Proposed System Block Diagram and Analysis 71 5.3 Circuit Implementation 75 5.3.1 Loop Filter 75 5.3.2 Rail-to-Rail Folded-Cascode Amplifier 77 5.3.3 VCM-based 6-bit SAR ADC 79 5.3.4 Sensing pixel 84 5.3.5 DC Current Cancellation Loop 86 5.4 Simulation Results 87 5.4.1 Layout chip 87 5.4.2 Simulation Results 88 5.5 Summary 93 Chapter 6 Conclusions and Future Works 94 6.1 Conclusions 94 6.2 Future Works 95 References 97 | - |
| dc.language.iso | en | - |
| dc.subject | 直流電流抵銷系統 | zh_TW |
| dc.subject | 三角積分調變器 | zh_TW |
| dc.subject | 多量化器 | zh_TW |
| dc.subject | 壓控震盪器 | zh_TW |
| dc.subject | 多輸入訊號感測器 | zh_TW |
| dc.subject | 偽偽差動 | zh_TW |
| dc.subject | 離子感測場效電晶體 | zh_TW |
| dc.subject | 類比前端電路 | zh_TW |
| dc.subject | Multi-Input Sensor | en |
| dc.subject | Pseudo Pseudo Differential | en |
| dc.subject | Dual Quantization | en |
| dc.subject | Delta-Sigma Modulator | en |
| dc.subject | Voltage-Controlled Oscillator | en |
| dc.subject | DC Current Cancellation System | en |
| dc.subject | Analog Front-End | en |
| dc.subject | ISFET | en |
| dc.title | 基於壓控振盪器以及多量化器之應用於電流偵測二階三角積分器設計 | zh_TW |
| dc.title | Design of 2nd-order Delta Sigma Modulators with Voltage-Controlled Oscillator and Dual Quantizer for Current Sensing | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 112-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 呂良鴻;蔡宗亨 | zh_TW |
| dc.contributor.oralexamcommittee | Liang-Hung Lu;Tsung-Heng Tsai | en |
| dc.subject.keyword | 離子感測場效電晶體,類比前端電路,直流電流抵銷系統,壓控震盪器,三角積分調變器,多量化器,偽偽差動,多輸入訊號感測器, | zh_TW |
| dc.subject.keyword | ISFET,Analog Front-End,DC Current Cancellation System,Voltage-Controlled Oscillator,Delta-Sigma Modulator,Dual Quantization,Pseudo Pseudo Differential,Multi-Input Sensor, | en |
| dc.relation.page | 103 | - |
| dc.identifier.doi | 10.6342/NTU202400951 | - |
| dc.rights.note | 未授權 | - |
| dc.date.accepted | 2024-05-10 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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