鐵電場效電晶體變異度及耐久性之分析

Abstract

這項研究全面分析了基於二氧化鉿(HfO2)的鐵電場效電晶體(ferroelectric field-effect transistor, FeFET)在元件和元件之間的變異度和耐久度問題。首先，我們研究了抹除電壓(erase voltage)對鐵電場效電晶體的變異度之影響。我們採用了系統性的脈衝方法進行分析，從結果可以發現鐵電場效電晶體的變異度與偶極子的切換和捕獲行為密切相關。因此，透過調整抹除電壓可以有效抑制鐵電場效電晶體的變異度。結果證明了在適當的抹除電壓下操作可以有效地降低高閾值電壓變異度(σHVT)，進而從128 mV降低到119 mV。除了改變操作電壓外，我們還透過in-situ NH3探討了元件界面優化對其變異度的影響。結果顯示界面優化有效地減少了TiN和HZO界面之間的氧空缺，從而降低了變異度。此外，對於記憶體應用而言，耐久性是一個關鍵且重要的指標。我們研究恢復技術啟用的最佳時機，以增強鐵電場效電晶體的耐久性，結果顯示使用恢復技術可以使耐久性週期延長100 倍。最後為了實現更高密度的鐵電記憶體，我們製造10奈米HZO的鰭式鐵電場效電晶體(FE-FinFET)。鰭式鐵電場效電晶體製造過程包括利用乾式蝕刻的方式定義主動區(active area)。乾式蝕刻定義主動區的過程會造成通道的側壁粗糙度上升，我們在相同的鐵電面積下，比較鰭式鐵電場效電晶體和平面鐵電場效電晶體之間的側壁數量差異，來評估蝕刻所引起的鰭式鐵電場效電晶體側壁損傷的影響。從量測的結果得知當通道寬度縮減並導致側壁損傷的比例增加時，捕獲行為會嚴重影響鐵電性的發揮，造成鰭式鐵電場效電晶體無法看到記憶視窗。當透過合成氣體退火(forming gas annealing)後，雖然鰭式鐵電場效電晶體依然無法看到記憶視窗，但從萃取出的閾值電壓(VTH) 和次臨界擺幅(SS)的變化幅度結果說明了合成氣體退火可以有效減少電子捕獲效應。此外，透過界面優化後，鰭式鐵電場效電晶體通道數量為50的時候，次臨界擺幅改善了33％ 並且明顯優於電晶體通道數為5 和20 的條件，這個結果顯示隨著側壁數量的增加，次臨界擺幅改善的趨勢更為明顯。以上兩個結果意味著合成氣體退火能夠有效修復界面處的陷阱。

This study comprehensively analyzes HfO2-based ferroelectric Metal Ferroelectric Insulator Semiconductors (MFIS), considering the device-to-device variability and endurance issues. First, we investigate the impact of erase voltage on the variability of ferroelectric field effect transistor (FeFET) devices. We employed a systematic pulsing methodology and demonstrated that the variability of FeFET devices is closely linked to the dipole switching and trapping behavior. Therefore, the variability of FeFET can be effectively controlled by adjusting the erase voltage. Our results indicate that operating at an appropriate voltage effectively reduced the threshold voltage variation (σHVT) from 128 mV to 119 mV. In addition to altering the operation voltage, we also explored the impact of device interface optimization on its variability via in-situ NH3 treatment. The results demonstrated that interface optimization effectively mitigates oxygen vacancies between the TiN and HZO surface, thereby reducing variation. Furthermore, endurance is a crucial indicator, especially for memory applications. We conducted a study to determine the recovery process to enhance the endurance of FeFETs. We applied a recovery treatment, resulting in a remarkable extension of endurance cycles by 102 times. Finally, we fabricated ferroelectric FinFET (FE-FinFET) based on 10 nm HZO to achieve higher-density ferroelectric memory. The manufacturing process of FE-FinFET included defining the active area through dry etching. We evaluated the impact of etching-induced damage on the sidewalls of FE-FinFETs by comparing sidewall numbers between FE-FinFET and planar FeFET structures with the same ferroelectric dimensions. Results from the measurements revealed that as the channel width decreases, leading to a higher proportion of sidewall damage, trapping effect behavior starts to influence the ferroelectric performance. Consequently, FE-FinFET becomes unable to exhibit a memory window. Even after forming gas annealing, FE-FinFET still failed to show a memory window. However, the extracted changes in threshold voltage (VTH) and subthreshold swing (SS) indicated that forming gas annealing effectively mitigates electron trapping effects. Furthermore, during interface optimization, especially when the channel number of FE-FinFETs was 50, the subthreshold swing improved by 33%, which is obviously better than the conditions where the number of transistor channels was 5 and 20. This result suggests that with an increase in sidewall numbers, the trend of improving subthreshold swing becomes more pronounced. Both outcomes imply that forming gas annealing excels in repairing traps at the interface.