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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 胡振國 | zh_TW |
dc.contributor.advisor | Jenn-Gwo Hwu | en |
dc.contributor.author | 林冠文 | zh_TW |
dc.contributor.author | Kuan-Wun Lin | en |
dc.date.accessioned | 2024-03-04T16:25:09Z | - |
dc.date.available | 2024-03-05 | - |
dc.date.copyright | 2024-03-04 | - |
dc.date.issued | 2022 | - |
dc.date.submitted | 2024-02-02 | - |
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Phys. 97 (12): 124506–1–124506–7, June 2005, doi:10.1063/1.1940134. [Ex7] W. M.Webster, “On the Variation of Junction-Transistor Current-Amplification Factor with Emitter Current,” Proc. IRE 42 (6): 914–920, 1954, doi:10.1109/JRPROC.1954/274751. [Ex8] Y. Taur & T. H. Ning. Fundamentals of Modern VLSI Devices. Cambridge University Press, Cambridge, 1998. [Ex9] A. D. Polyanin & V. F. Zaitsev. Handbook of Ordinary Differential Equations: Exact Solutions, Methods, and Problems, 3 ed. CRC Press, 2017. [Ex10] W. Kutta, “Beitrag zur Näherungsweisen Integration Totaler Differentialgleichungen,” Z. Math. Phys. 46: 434–453, 1901. [Ex11] G. F. Becker & C. E. van Orstrand. Smithsonian Mathematical Tables: Hyperbolic Functions. University of Michigan Library, 1909. | - |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/92079 | - |
dc.description.abstract | 本論文詳細研究具超厚薄氧化層之鋁/二氧化矽/p型矽金氧半穿隧元件(或稱超厚薄元件,即氧化層在特定區域為超薄,其餘為超厚)的電特性、靜電學特性和其中的載子傳輸機制。首先,我們對真實元件進行量測與定性研究,並以TCAD模擬輔助觀察。吾人發現元件施加反偏壓時,儘管載子穿隧只在薄氧區發生,穿隧電流卻正比於閘極面積,而非薄氧區面積。換言之,金氧半電容氧化層中的微小局部薄化區域(只佔閘極面積的百萬分之幾)便可導致巨大的漏流,顯示了氧化層品質控制的重要。我們將此現象歸因於一種新發現的、反轉電荷的水平耦合機制,能將厚氧區中的電子耗盡,從而影響其靜電學特性,影響範圍深遠。為定量探討這些發現,吾人首次提出一個適用於較簡單平面結構—金氧半穿隧二極體—的靜電學解析模型。本模型顯示了此平面結構的靜電學特性在某個臨界偏壓前後截然不同,而吾人也推導出此臨界偏壓對氧化層厚度的閉形近似式。模型與TCAD模擬結果高度吻合(誤差小於2 Å),並成功重現金氧半穿隧二極體的實驗特性。隨後,本模型被推廣至超厚薄元件中,尤其著重厚氧區中電子準費米能階的建模,而成功預測前述穿隧電流正比於閘極面積的現象,以及前述耦合機制的作用距離超過毫米等級。這些模型有助我們從物理和直觀的面向加深對金氧半穿隧二極體與超厚薄元件的瞭解。最後,吾人探討以超厚薄元件作為溫度與環境光感測器之應用。在低偏壓(不高於0.3伏特)之下,與平面的金氧半穿隧二極體相比,超厚薄元件的溫度響應度與光電流均提升超過百倍,顯示其具有作為低電壓下感測器應用的潛力。 | zh_TW |
dc.description.abstract | The electrical characteristics, electrostatics, and carrier transport mechanisms in Al/SiO2/Si(p) metal-oxide-semiconductor (MOS) tunnel structures with ultra-high-low oxides (the “ultra-high-low devices”, where the oxide layer is ultrathin at specific locations and ultrathick otherwise) have been comprehensively studied in this dissertation. First, a qualitative study has been conducted on characterizing experimental devices with an aid of TCAD simulation. Under reverse bias, device tunnel currents were found proportional to the gate area rather than the low-region area, even though carrier tunneling only occurs at the low region. In other words, a tiny local oxide thinning spot (accounting only millionths of the gate area) in an MOS capacitor can lead to a giant gate leakage, affirming the importance of oxide quality control. This phenomenon was ascribed to a newly-discovered lateral electron coupling mechanism, which is capable of depleting electrons in the high region and affecting the electrostatics thereof over a wide distance. To study these findings quantitatively, an analytical electrostatics model for the degenerate planar structures, metal-oxide-semiconductor tunnel diodes (MIS TDs), under reverse bias was established the first time. The model reveals a critical gate voltage that demarcates the electrostatics into two dissimilar regimes. A closed-form approximation for the critical voltage-oxide thickness relation was then derived. The model highly agrees with TCAD simulation results (with <2 Å discrepancy) and manages to reproduce the experimental MIS TD characteristics. Subsequently, the model was generalized into ultra-high-low devices with an emphasis on modeling the electron quasi Fermi level in the high region. It successfully predicts the aforementioned gate area proportionality of the tunnel current, as well as a lateral coupling distance beyond the millimeter scale. The models may help us understand MIS TDs and ultra-high-low structures in a more physical and intuitive aspect. Finally, temperature and ambient light sensor applications for the ultra-high-low devices were investigated. Compared to a planar MIS TD, the thermal responsivity and photocurrent in an ultra-high-low device can be increased > 100-fold under low applied bias (no greater than 0.3 V), making them a competitive candidate for low-voltage sensor applications. | en |
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dc.description.tableofcontents | Acknowledgments (Chinese) … vii
Abstract (Chinese) … ix Abstract (English) … xi Abstract (Latin) … xiii Table of Contents … xv List of Figures … xix List of Tables … xxxi Nomenclature … xxxiii 1. Introduction … 1 1.1 Motivation … 1 1.2 Current-Voltage Characteristics and Electrostatics for Planar Al/SiO2/Si(p) MIS Tunnel Diodes … 5 1.3 High-Low and Ultra-High-Low MOS Tunnel Structures … 12 1.4 On Fabricating the High-Low Oxide Structures … 13 1.5 Dissertation Organization … 17 2. Qualitative Study on Electrical Characteristics, Electrostatics, and Carrier Transport Phenomena in Ultra-High-Low MOS(p) Tunnel Structures … 19 2.1 Background … 20 2.2 Experimental Details … 20 2.3 Results and Discussion … 23 2.3.1 Experimental Current-Voltage and Capacitance-Voltage Characteristics … 23 2.3.2 TCAD Simulation Results … 30 2.3.3 Low Area Proportion and Oxide Thickness Effects … 43 2.3.4 Prominence of Deep Depletion in Aggressively-Scaled High-Low Devices … 49 2.4 Summary … 49 3. Electrostatics Theory and Modeling I: Planar MIS(p) Tunnel Diodes Under Reverse Bias … 53 3.1 Background … 53 3.2 The Model and Procedure for Evaluation … 56 3.2.1 Electron Current Components … 59 3.2.2 Potentials and Surface Charge … 63 3.2.3 Procedure for Evaluation … 63 3.3 Experimental Details … 65 3.4 Results and Discussion … 67 3.5 A Closed-Form Approximation for the Critical Voltage vs. Oxide Thickness Relation … 81 3.6 Summary … 85 4. Electrostatics Theory and Modeling II: Ultra-High-Low MOS(p) Tunnel Structures Under Reverse Bias … 87 4.1 Objective … 87 4.2 High-Region Generation Current Model for Cylindrically-Symmetric UHL Devices … 88 4.2.1 High-Region Surface Band Bending … 89 4.2.2 Electron QFL, Carrier Generation, and Electron Coupling in the High Region … 90 4.3 Generalization of the Planar Electrostatics Model into Cylindrically-Symmetric UHL Structures … 94 4.4 Summary … 101 5. Low-Voltage Sensor Applications for Ultra-High-Low MOS(p) Tunnel Structures Utilizing Intensified Schottky Barrier Height Modulation Effect … 103 5.1 Background … 104 5.2 Experimental Details … 105 5.3 Results and Discussion … 106 5.3.1 Electrical Characteristics and Schottky Barrier Height Extraction … 106 5.3.2 Temperature Sensor Applications … 112 5.3.3 Ambient Light Sensor Applications … 114 5.4 Summary … 119 6. Conclusions and Future Works … 121 6.1 Conclusions … 121 6.2 Suggestions for Future Works … 122 Appendix A. Minority Carrier Quasi Fermi Level in Space Charge Region Considering Shockley-Read-Hall Generation … 125 A.1 Motivation … 125 A.2 Minority Quasi Fermi Level to A Linear Differential Equation Problem … 126 A.3 Electron Quasi Fermi Level in One-Dimensional MIS(p) Tunnel Diodes Under Reverse Bias … 131 A.4 Electron Quasi Fermi Level in Cylindrically-Symmetric Ultra-High-Low MOS(p) Devices Under Reverse Bias … 142 A.5 Summary … 153 References … 155 Excursus. General Modeling of p-n Diode Electrostatics and Currents Under Forward Bias for All Injection Levels … 165 | - |
dc.language.iso | en | - |
dc.title | 具超厚薄氧化層之鋁/二氧化矽/p型矽金氧半穿隧結構研究 | zh_TW |
dc.title | Study on Al/SiO2/Si(p) Metal-Oxide-Semiconductor Tunnel Structures with Ultra-High-Low Oxides | en |
dc.type | Thesis | - |
dc.date.schoolyear | 112-1 | - |
dc.description.degree | 博士 | - |
dc.contributor.oralexamcommittee | 曾俊元;王永和;蘇彬;陳敏璋;連振炘;林浩雄 | zh_TW |
dc.contributor.oralexamcommittee | Tseung-Yuen Tseng;Yeong-Her Wang;Pin Su;Miin-Jang Chen;Chen-Shin Lien;Hao-Hsiung Lin | en |
dc.subject.keyword | 解析模型,深空乏,靜電學,反轉電荷,金氧半穿隧二極體,金氧半電容,氧化層軟崩潰,氧化層穿隧,感測器, | zh_TW |
dc.subject.keyword | Analytical model,Deep depletion,Electrostatics,Inversion charge,MIS tunnel diode,MOS capacitor,Oxide soft breakdown,Oxide tunneling,Sensors, | en |
dc.relation.page | 227 | - |
dc.identifier.doi | 10.6342/NTU202304241 | - |
dc.rights.note | 同意授權(全球公開) | - |
dc.date.accepted | 2024-02-04 | - |
dc.contributor.author-college | 電機資訊學院 | - |
dc.contributor.author-dept | 電子工程學研究所 | - |
顯示於系所單位: | 電子工程學研究所 |
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