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DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 李建模 | zh_TW |
dc.contributor.advisor | Chien-Mo Li | en |
dc.contributor.author | 黃旭鈺 | zh_TW |
dc.contributor.author | Hsu-Yu Huang | en |
dc.date.accessioned | 2024-02-22T16:18:43Z | - |
dc.date.available | 2024-02-23 | - |
dc.date.copyright | 2024-02-22 | - |
dc.date.issued | 2024 | - |
dc.date.submitted | 2024-02-01 | - |
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dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/91702 | - |
dc.description.abstract | 得益於低功耗特性,神經形態晶片為一種具發展潛力的人工智慧應用硬體實現。然而由於具多種潛在配置卻缺乏可測試性設計,神經形態晶片的測試十分困難。我們提出一種不需可測試性設計的神經形態晶片演算法測試生成方法,包含錯誤激活和錯誤傳播。錯誤激活使一個神經元的正確輸出和錯誤輸出差異化。錯誤傳播活化錯誤效應,使得錯誤晶片和良好晶片的輸出差異化。
我們提出的方法有以下三種優勢。其一,我們以低測試複雜度達到高錯誤覆蓋率。其二,我們考慮權重量化與權重變異的影響。最後,經由理論分析,我們保證錯誤覆蓋率及測試複雜度。在可忽略和無權重變異條件下,我們在脈衝神經網路模型上達到100% 錯誤覆蓋率,並且所需的測試配置和測試樣本數目僅和神經元層數成正比。結果顯示即使權重被量化至四位元,我們的方法依然維持測試有效性。當小於10% 權重變異時,我們沒有造成任何的測試逃脫及過度測試。我們的整體測試長度相較於先前研究減低了超過七萬三千倍。 | zh_TW |
dc.description.abstract | Neuromorphic chips are promising hardware implementations for artificial intelligence (AI) applications owing to their low power consumption. However, neuromorphic chips are difficult to test since they have many potential configurations but lack design for testability (DfT). We propose an algorithmic test generation method for neuromorphic chips without DfT, including fault activation and fault propagation. Fault activation differentiates a neuron’s good output and faulty output. Fault propagation sensitizes fault effects to differentiate outputs of faulty chips and good chips.
The proposed method has three advantages. First, we achieve high fault coverage with low test complexity. Second, we consider the influence of weight quantization and weight variation. Lastly, we guarantee fault coverage and test complexity by theoretical analysis. On an L-layer Spiking Neural Network (SNN) model, we achieve 100% fault coverage using O(L) test configurations and test patterns under negligible or no weight variation. Our results show that test effectiveness is maintained even with 4-bit weight quantization. We incur no test escape and overkill even under 10% weight variation. Our total test length is over 73k times shorter than previous works. | en |
dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2024-02-22T16:18:43Z No. of bitstreams: 0 | en |
dc.description.provenance | Made available in DSpace on 2024-02-22T16:18:43Z (GMT). No. of bitstreams: 0 | en |
dc.description.tableofcontents | 口試委員審定書 i
致謝 ii 摘要 iii Abstract iv Contents vi List of Figures ix List of Tables xi Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Proposed Techniques 5 1.3 Contributions 7 1.4 Organization 8 Chapter 2 Background 9 2.1 Neuromorphic chips 9 2.2 Testing Neuromorphic Chips 10 2.3 Spiking Neural Network (SNN) 14 2.4 SNN Fault Models 16 Chapter 3 Proposed Test Generation 18 3.1 Overview 20 3.2 Fault Activation 22 3.2.1 NASF and SASF 22 3.2.2 ESF, HSF, and SWF 22 3.2.2.1 ESF and HSF 23 3.2.2.2 SWF 25 3.3 Fault Propagation 28 3.4 Fault Detection 31 Chapter 4 Test Complexity 35 4.1 Calculation of ν 35 4.1.1 ESF and HSF 36 4.1.2 SWF 37 4.2 Analysis of test complexity 38 Chapter 5 Experimental Results 42 5.1 Settings 42 5.2 Test generation results 43 5.3 Test effectiveness under weight variation 44 Chapter 6 Discussion 48 6.1 Test generation for ANN 48 6.1.1 Neuron faults 48 6.1.2 Synapse faults 50 6.1.3 Fault detection 50 6.2 Timing variation of spike transmission 51 Chapter 7 Conclusion 52 References 54 Appendix A — Notation 60 | - |
dc.language.iso | en | - |
dc.title | 神經形態晶片的低複雜度演算法測試生成 | zh_TW |
dc.title | Low-Complexity Algorithmic Test Generation for Neuromorphic Chips | en |
dc.type | Thesis | - |
dc.date.schoolyear | 112-1 | - |
dc.description.degree | 碩士 | - |
dc.contributor.oralexamcommittee | 劉宗德;呂學坤 | zh_TW |
dc.contributor.oralexamcommittee | Tsung-Te Liu;Shyue-Kung Lu | en |
dc.subject.keyword | 神經形態晶片,脈衝神經網路,測試配置生成,測試樣本生成,常數可測試, | zh_TW |
dc.subject.keyword | Neuromorphic chips,Spiking Neural Network,Test configuration generation,Test pattern generation,C-testable, | en |
dc.relation.page | 60 | - |
dc.identifier.doi | 10.6342/NTU202400172 | - |
dc.rights.note | 同意授權(全球公開) | - |
dc.date.accepted | 2024-02-04 | - |
dc.contributor.author-college | 電機資訊學院 | - |
dc.contributor.author-dept | 電子工程學研究所 | - |
顯示於系所單位: | 電子工程學研究所 |
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