分析隨機相位分佈對於層壓型鐵電場效電晶體 記憶體變異度之影響

Abstract

鐵電場效電晶體(ferroelectric field-effect transistor, FeFET)作為新興記憶體，具有非揮發性，與CMOS製程相容等優點，並且也可以透過鐵電材料的特性達到多位元儲存的功能，因此被認為極有潛力運用於記憶體內運算，做為深度神經網路裡面的突觸，並展現可調變權重特性。然而，鐵電場效電晶體因為鐵電材料的影響導致變異度變成了非常重要的課題，本篇論文考慮隨機相位分布對於層壓型(laminated)鐵電場效電晶體變異度之影響，透過MATLAB產生隨機分布的鐵電-介電相晶粒，並套用至TCAD軟體內進行不同鐵電百分比的模擬，分析在不同鐵電百分比之下，層壓型鐵電場效電晶體與傳統單層鐵電場效電晶體的變異度差異。 鐵電場效電晶體可應用於記憶體元件和突觸元件，本篇論文首先研究鐵電場效電晶體在記憶體性能的表現，記憶體視窗(memory window, MW)為鐵電記憶體重要的電性指標，結果顯示在元件通道尺寸為80 nm × 80 nm時，相較單層鐵電場效電晶體，層壓型鐵電場效電晶體在鐵電百分比較低時 (50%和62.5%)，可以分別改善15.4%和41%的記憶體視窗變異度;而在鐵電百分比較高時 (75%和81.25%)，層壓型鐵電場效電晶體的記憶體視窗變異度會較單層鐵電場效電晶體高;當元件通道尺寸微縮至40 nm × 40 nm時，層壓型鐵電場效電晶體在無論較高或較低的鐵電百分比下，層壓型鐵電場效電晶體的記憶體視窗之變異度都能夠較傳統單層鐵電場效電晶體小，由此可知，層壓型鐵電場效電晶體在尺寸持續微縮的趨勢下能夠改善記憶體視窗之變異度。 接著，本篇論文探討鐵電場效電晶體做為突觸元件之特性，觀察隨機相位分布對突觸的權重校正線性度，可以從結果發現，讀取電壓從0.5V增加至0.9V，線性度會逐漸上升，而當讀取電壓為0.9V時，達到最理想(最接近零)的線性度，最佳線性度所對應到的讀取電壓會落在次臨界區和超臨界區的交界。另外，增加讀取電壓從0.5V增加至0.9V，鐵電百分比為50%和75%下，層壓型鐵電場效電晶體的線性度以及線性度之變異度皆較單層鐵電場效電晶體為理想，更適合用於模擬深度神經網絡。

Ferroelectric Field-Effect Transistors (FeFETs) are emerging non-volatile memory devices with advantages such as compatibility with CMOS processes and the potential for multi-bit storage through ferroelectric material properties. Consequently, they are considered promising for in-memory computation within deep neural networks, serving as synapses and exhibiting adjustable weight characteristics. However, the variability of FeFETs due to ferroelectric material effects has become a significant concern. This paper addresses the impact of random phase distribution on the variability of laminated ferroelectric field-effect transistors. Using MATLAB, random distributions of ferroelectric-dielectric phase grains are generated and applied to TCAD software to simulate devices with different ferroelectric percentages. The variations in laminated ferroelectric field-effect transistors are analyzed under various ferroelectric percentages and compared with traditional single-layer ferroelectric field-effect transistors. Ferroelectric field-effect transistors find applications in memory and synaptic devices. This paper first investigates the performance of ferroelectric field-effect transistors in memory applications. The memory Window (MW) is a crucial electrical indicator for ferroelectric memory, and the results show that for a device channel size of 80 nm × 80 nm, compared to single-layer ferroelectric field-effect transistors, laminated ferroelectric field-effect transistors exhibit improvements of 15.4% and 41% in MW variation for lower ferroelectric percentages (50% and 62.5%), and higher MW variation for higher ferroelectric percentages (75% and 81.25%). When the device channel size scales down to 40 nm × 40 nm, laminated ferroelectric field-effect transistors consistently show smaller MW variations than traditional single-layer ferroelectric field-effect transistors, regardless of the ferroelectric percentage. This indicates that laminated ferroelectric field-effect transistors can mitigate MW variation trends as the size continues to decrease. Furthermore, this paper explores the characteristics of ferroelectric field-effect transistors as synaptic devices. The influence of random phase distribution on the linearity correction of synaptic weights is examined. The results show that increasing the read voltage from 0.5V to 0.9V gradually improves linearity, with the most ideal linearity achieved at 0.9V. The optimal linearity corresponds to the boundary between the subthreshold and superthreshold regions. Additionally, under ferroelectric percentages of 50% and 75%, increasing the read voltage to 0.9V results in better linearity and reduced variability in linearity for laminated ferroelectric field-effect transistors compared to single-layer counterparts, making them more suitable for simulating deep neural networks.