應用於6G通訊具LO I/Q相位校正之240 GHz次太赫茲CMOS發射機

Abstract

6G預計可以提供超過100 Gb/s的資料傳輸速率，因此需要使用到太赫茲的頻段來獲得大量的頻寬。然而太赫茲收發機仍然面臨許多挑戰如製程限制。40-nm CMOS的fmax約為260~290 GHz，故操作在200 GHz以上的發射機無法實現傳統的功率放大器後架構。本論文提出一個240 GHz發射機，使用混頻器後的架構以確保系統可以提供高階數位調變，並使用直接升頻的方式來減少系統複雜度。 第二章呈現了一個235 GHz的倍頻鏈，由一個疊接功率放大器和三倍頻器所組成。其中三倍頻器使用自混和最佳諧波阻抗匹配的技巧可以提升5.7 dBm的模擬輸出功率。在234 GHz時，量測的峰值轉換增益為-5 dBm、輸出功率為-5.4 dBm而3-dB頻寬為34 GHz。 第三章將此倍頻鏈整合進發射機的LO端並加入相位校正機制，同時說明耦合器和混頻器的設計以及晶片封裝。在240 GHz時，量測的轉換增益為-14.2 dB、1-dB壓縮點為-15.7 dBm、RF輸出頻寬為20 GHz、LO洩漏為-25 dBc、鏡像抑制比為-33.5 dB。有線資料傳輸的量測受到儀器的限制，最高的資料傳輸速率為400 Mb/s使用16QAM的調變方式。在驗證此發射機的性能後加入一個240 GHz的功率放大器來提升發射機的輸出功率。此放大器最佳化電晶體佈局可以改善fmax至380 GHz，另外使用嵌入式網路來增加增益。量測結果顯示峰值轉換增益的頻率飄移至220 GHz以下，因此仍需改善功率放大器的電晶體模型和設計。

6G is expected to provide the data rate exceeding 100 Gb/s, necessitating the use of the terahertz frequency range to achieve significant bandwidth. However, terahertz transceivers still face various challenges, such as process limitations. The fmax of 40-nm CMOS is approximately 260-290 GHz, making it challenging to achieve traditional PA-last transmitters above 200 GHz. This paper proposes a 240 GHz transmitter using mixer-last architecture to ensure the system can support high-level digital modulation and employs direct up-conversion to reduce system complexity. Chapter 2 presents a 235 GHz frequency multiplier chain consisting of a cascode power amplifier and a tripler. The tripler utilizes self-mixing and optimal harmonic impedance matching techniques, resulting in a simulated output power improvement of 5.7 dBm. The measured peak conversion gain at 234 GHz is -5 dBm, with an output power of -5.4 dBm and a 3-dB bandwidth of 34 GHz. Chapter 3 integrates the frequency tripler chain into the LO of transmitter, and introduces a phase calibration mechanism. The design of coupler, mixer and packaging will also be explained. At 240 GHz, the measured conversion gain is -14.2 dB, the 1-dB compression point is -15.7 dBm, RF bandwidth is 20 GHz, LO leakage is -25 dBc, and image rejection ratio is -33.5 dB. The limitation of instrument constrains the wired data transmission measurement, resulting in a highest data rate of 400 Mb/s with 16QAM modulation. After validating the transmitter’s performance, a 240 GHz power amplifier is added to enhance the transmitter's output power. Optimization of the transistor layout in this amplifier improves fmax to 380 GHz, and embedded networks are employed to increase gain. Measurement results indicate that the peak conversion gain frequency has shifted below than 220 GHz. Therefore, improvements are necessary in the design and modeling of the power amplifier