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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 李泰成 | zh_TW |
dc.contributor.advisor | Tai-Cheng Lee | en |
dc.contributor.author | 黃士杰 | zh_TW |
dc.contributor.author | Shih-Jie Huang | en |
dc.date.accessioned | 2024-01-26T16:16:14Z | - |
dc.date.available | 2024-01-27 | - |
dc.date.copyright | 2024-01-26 | - |
dc.date.issued | 2023 | - |
dc.date.submitted | 2024-01-15 | - |
dc.identifier.citation | [1] J. Lagos, B. Hershberg, E. Martens, P. Wambacq, and J. Craninckx, “A Single-Channel, 600-MS/s, 12-b, Ringamp-Based Pipelined ADC in 28-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 54, pp. 403–416, Feb. 2019.
[2] B. Hershberg, S. Weaver, K. Sobue, S. Takeuchi, K. Hamashita, and U.K. Moon, “Ring Amplifiers for Switched Capacitor Circuits,” IEEE Journal of Solid-State Circuits, vol. 47, pp. 2928–2942, Dec. 2012. [3] C.-C. Liu, Design of High-Speed Energy-Efficient Successive-Approximation Analog-to-Digital Converters. Ph.D. dissertation, National Cheng Kung University, 2010. [4] C.-C. Liu, S.-J. Chang, G.-Y. Huang, and Y.-Z. Lin, “A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure,” IEEE Journal of Solid-State Circuits, vol. 45, pp. 731–740, Apr. 2010. [5] B. Wicht, T. Nirschl, and D. Schmitt-Landsiedel, “Yield and speed optimization of a latch-type voltage sense amplifier,” IEEE Journal of Solid-State Circuits, vol. 39, pp. 1148–1158, July 2004. [6] B. Murmann, “ADC Performance Survey 1997-2023.” [Online]. Available: https://web.stanford.edu/~murmann/adcsurvey.html, 2023. [7] J. Lagos, B. P. Hershberg, E. Martens, P. Wambacq, and J. Craninckx, “A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers,” IEEE Journal of Solid-State Circuits, vol. 54, pp. 646–658, Mar. 2019. [8] W. Jiang, Y. Zhu, M. Zhang, C.-H. Chan, and R. P. Martins, “A Temperature-Stabilized Single-Channel 1-GS/s 60-dB SNDR SAR-Assisted Pipelined ADC With Dynamic Gm-R-Based Amplifier,” IEEE Journal of Solid-State Circuits, vol. 55, pp. 322–332, Feb. 2020. [9] H.-H. Chang, T.-C. Lin, and T.-C. Lee, “A Single-Channel 1-GS/s 7.48-ENOB Parallel Conversion Pipelined SAR ADC With a Varactor-Based Residue Amplifier,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, pp. 2021–2025, Apr. 2022. | - |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/91385 | - |
dc.description.abstract | 本篇論文提出一個無須補償之兩級放大器,相較於傳統放大器,除了無須補償電容之外,其具有高迴轉率以及開關控制,使其具高速和低功耗的優點。此放大器被應用在導管式-循序漸進式類比數位轉換器中。此外,提出的轉換器使用平行比較架構,加速其運算,以此達成十億赫茲的取樣頻率。
本晶片使用台積電28奈米製程下線,總面積為1.00平方毫米。量測中,在十億赫茲的取樣頻率下,可測得52.01分貝的訊號對雜訊失真比,同時僅消耗7.99毫瓦。 | zh_TW |
dc.description.abstract | A compensation-free two-stage amplifier is proposed in this thesis. Compared to traditional operational amplifiers, the compensation capacitor can be omitted. Also, the proposed amplifier has high slew rate and can be turned off when idle, leading to its high-speed and low-power feature. This amplifier is adopted in a pipelined-SAR ADC, where parallel conversion architecture is applied to accelerate the conversion rate to reach a sampling rate of 1 GS/s.
The chip is fabricated with 28 nm process. The total area is 1.00 mm2. In measurement, under sampling rate of 1 GS/s, the proposed ADC has an SNDR of 52.01 dB and consumes 7.99 mW. | en |
dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2024-01-26T16:16:14Z No. of bitstreams: 0 | en |
dc.description.provenance | Made available in DSpace on 2024-01-26T16:16:14Z (GMT). No. of bitstreams: 0 | en |
dc.description.tableofcontents | 誌謝 iii
摘要 iv Abstract v Contents vi List of Figures ix List of Tables xi 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Structure 1 2 Fundamental 3 2.1 Introduction 3 2.2 ADC Performance Metrics 3 2.2.1 Bandwidth 3 2.2.2 SNR 4 2.2.3 SNDR 4 2.2.4 SFDR 5 2.2.5 ENOB 5 2.2.6 FoM 5 2.2.7 DNL 5 2.2.8 INL 6 3 System Architecture and Implementation 7 3.1 System Overview 7 3.2 MDAC 10 3.3 Proposed Amplifier 11 3.4 Other Building Blocks 25 3.4.1 Bootstrapped Switch 25 3.4.2 Comparator 26 3.4.3 SAR Control Logic 27 3.4.4 Capacitor DAC 28 3.4.5 Clock Generator 29 3.5 Simulation Results 29 4 Analysis 32 4.1 C-DAC Unit Capacitance Consideration 32 4.2 Noise Analysis 34 4.2.1 Comparator Noise 34 4.2.2 Amplifier Noise 36 4.3 Offset Analysis 37 4.3.1 Comparator Offset 37 5 Experimental Result 39 5.1 Printed Circuit Board Design 39 5.2 Measurement Setup 41 5.3 Experimental Result 41 6 Conclusion 46 6.1 Comparison Table 46 6.2 Conclusion 46 Bibliography 48 | - |
dc.language.iso | en | - |
dc.title | 使用無須頻率補償之二級放大器實作的導管式循序漸進式類比數位轉換器 | zh_TW |
dc.title | A Pipelined-SAR ADC with Compensation-Free Two-Stage OPAMP | en |
dc.type | Thesis | - |
dc.date.schoolyear | 112-1 | - |
dc.description.degree | 碩士 | - |
dc.contributor.oralexamcommittee | 陳信樹;鍾勇輝;劉深淵 | zh_TW |
dc.contributor.oralexamcommittee | Hsin-Shu Chen;Yung-Hui Chung;Shen-Iuan Liu | en |
dc.subject.keyword | 二級放大器,環形放大器,無須頻率補償,導管式循序漸進式類比數位轉換器,平行轉換, | zh_TW |
dc.subject.keyword | Two-Stage Amplifier,Ring Amplifier,Frequency-Compensation-Free,Pipelined-SAR Analog-to-Digital Converters,Parallel Conversion, | en |
dc.relation.page | 49 | - |
dc.identifier.doi | 10.6342/NTU202400074 | - |
dc.rights.note | 同意授權(限校園內公開) | - |
dc.date.accepted | 2024-01-16 | - |
dc.contributor.author-college | 電機資訊學院 | - |
dc.contributor.author-dept | 電子工程學研究所 | - |
顯示於系所單位: | 電子工程學研究所 |
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