透過引入底部介電質隔離技術改善航太應用的抗輻射靜態隨機存取記憶體

Abstract

近年來，電晶體技術的發展取得了令人瞩目的突破，對抗輻射元件的發展和應用領域產生了廣泛而深遠的影響。隨著航太技術的不斷進步和低軌道衛星的廣泛應用，對於抗輻射元件的需求日益迫切。在高能粒子和輻射衝擊所帶來的嚴酷環境中，傳統的電子元件容易受到損壞，從而導致系統性能下降甚至失效。為了應對這一挑戰，抗輻射元件應運而生，旨在提供更高的輻射容忍度，以確保系統在極端環境下的可靠性和穩定性。 本篇論文提出了一種將部分底部介電質隔離技術應用於抗輻射(Radiation-Hardened)靜態隨機存取記憶體(static random-access memory, SRAM)的技術。本篇論文首先基於國際元件與系統技術藍圖(International Roadmap for Devices and Systems, IRDS)所提供的結構以及材料參數，分析無接面式 (junctionless mode)與反轉式 (inversion mode)通道在超薄型矽覆蓋絕緣層(Ultra-Thin Body Silicon-On-Insulator, UTBSOI)與雙閘極(Double Gate, DG)場效電晶體結構的抗輻射特性，以及奈米片場效電晶體(Nanosheet FET, NSFET)對高能粒子入射之方向與位置之收集電荷(collected charge)之比較，以此得出元件受輻射影響最劇之情況，接著分析二種類型的深埋層氧化物技術應用在奈米片電晶體中抗輻射能力之改善程度 : (1)部分底部介電質隔離奈米片電晶體(Partial Bottom Dielectric Isolation NSFET , PDI-NSFET)；(2) 閘極底部深埋層氧化物電晶體(Buried Oxide NSFET , BO-NSFET) 。論文最後分析6T SRAM與12T寫入增強式四儲存節點(Writability Enhanced Quatro, We-Quatro) SRAM之抗幅射能力，研究使用部分底部介電質隔離技術在抗幅射應用之成效。 研究結果顯示採用部分底部介電質隔離(PDI)之奈米片電晶體，在收集電荷上比起傳統使用純矽基板(silicon substrate)的奈米片電晶體減少了55%，而使用閘極底部深埋層氧化物奈米片電晶體(BO-NSFET)亦可以減少41%收集電荷。在靜態隨機存取記憶體方面，使用PDI的6T SRAM能較不使用PDI 的12T We-Quatro SRAM減少57%的面積，並且能多容忍56%更高線性能量轉移 (Linear Energy Transfer, LET)粒子入射，使資料不會出現錯誤翻轉，提升航太應用中電子元件的可靠度與效能。

In recent years, there have been remarkable breakthroughs in transistor technology, which have had a widespread and profound impact on the development and application of radiation-hardened components. With advancements in aerospace technology and the extensive use of low Earth orbit (LEO) satellites, the demand for radiation-tolerant components has become increasingly urgent. In the harsh environments created by high-energy particles and radiation impacts, traditional electronic components are prone to damage, resulting in performance degradation or even system failure. To address this challenge, radiation-hardened components have emerged, aiming to provide higher radiation tolerance and ensure reliability and stability in extreme conditions.

This thesis presents a technique that applies partial bottom dielectric isolation to radiation-hardened Static Random-Access Memory (SRAM). Based on the structure and material parameters specified in the International Roadmap for Devices and Systems (IRDS), this thesis compares the collected charge from junctionless mode and inversion mode in Ultra-Thin Body Silicon-On-Insulator (UTB SOI) and Double Gate Field-Effect Transistor (Double Gate FET) structures, as well as Nanosheet FET (NSFET), in response to high-energy particle incidence angle and position. The analysis identifies the scenarios in which the devices are most affected by radiation. The thesis then proceeds to analyze the improvement of radiation tolerance in Nanosheet FET considering two types of buried oxide techniques: Partial Bottom Dielectric Isolation NSFET (PDI-NSFET) and Bottom Gate Buried Oxide NSFET (BO-NSFET). Finally, the effectiveness of using partial bottom dielectric isolation in comparison to conventional 6T SRAM and 12T Writability Enhanced Quatro (We-Quatro) SRAM is analyzed.

The research results show that NSFET with partial bottom dielectric isolation (PDI) reduces the collected charge by 55% compared to the traditional NSFET with a pure silicon substrate. Similarly, the use of BO-NSFET also reduces the collected charge by 41%. In terms of SRAM, the 6T SRAM with PDI achieves a 57% area reduction compared to radiation-hardened 12T We-Quatro SRAM without PDI, while tolerating 56% higher energy particle incidence without data flipping. 6T SRAM with PDI enhances the reliability and performance of electronic components for aerospace applications.