低溫靜態隨機存取記憶體應用於高效能運算之優化

Abstract

隨著製程技術的發展，同時降低供應電壓與臨界電壓會導致整體電路的靜態功率嚴重增加以及穩定性下降，使得互補式金氧半場效電晶體(complementary metal-oxide semiconductor, CMOS)元件的微縮碰到一定的困難，此外，隨著摩爾定律持續的演進，後段製程金屬導線電阻值會快速的增加，進而降低電路的效能。低溫CMOS是一個極有潛力解決效能下降問題的技術，透過將元件操作在低溫的環境下，在提高電路性能的同時也能降低功率消耗。然而，將低溫CMOS操作在低供應電壓與低臨界電壓的條件下，依然面臨穩定性不足的挑戰，因此，需要利用設計技術協同優化(design technology co-optimization, DTCO)來同時改善性能和穩定度。本論文考慮低溫矽鰭式場效電晶體(Si FinFET)之電流電壓實驗數據，並與TCAD模型進行校正，分析6T和8T靜態隨機存取記憶體(static random-access memory, SRAM)在低溫下的性能表現，分析讀寫穩定度和速度等特性，最後提出在77K下6T與8T SRAM的優化設計。 本論文分析並比較經過優化後的6T opt2、Opt 6N2P 8T與Opt-LVR 4N4P 8T三種SRAM，研究結果顯示Opt-LVR 4N4P 8T SRAM在各方面的性能上都優於其他的記憶體設計，與77K 6T LVT相比，Opt-LVR 4N4P 8T SRAM提升讀取穩定度達540%、寫入穩定度達78%，在讀取時間(-40%)與能量消耗(-61%)上，相較於300K 6T Baseline SRAM皆有更好的表現，儘管77K Opt-LVR 4N4P 8T SRAM有著面積較大的劣勢，仍能利用積層型三維(Monolithic 3D, M3D)堆疊技術來克服此問題，其4顆N型與4顆P型元件所組成SRAM電路，在積層型三維堆疊技術中，可以利用一層N型元件及一層P型元件的堆疊方式，使整體面積達到40%的下降，解決面積過大的問題。 此外與300K 6T Baseline的SRAM相比，Opt-LVR 4N4P 8T SRAM在相同功率下具有顯著的速度增益（+45%），在相同速度下也表現較低的功率消耗（-73%）。Opt-LVR 4N4P 8T SRAM在供應電壓降到0.45V時，仍有不錯的速度表現及並降低73%的功率消耗，具備高潛力應用於高效能運算應用。

As the process technology advances, simultaneous reduction of supply voltage and threshold voltage results in a significant increase in overall circuit static power and a decline in stability. This poses challenges for scaling Complementary Metal-Oxide-Semiconductor (CMOS) devices. Furthermore, with the continued evolution of Moore's Law, the metal wire resistance in the Back-End-of-Line(BEOL) process increases rapidly, leading to decreased circuit performance. Low-temperature CMOS is a promising technique to address this performance degradation issue, achieved by operating components in a low-temperature environment, which enhances circuit performance while reducing power consumption. However, operating low-temperature CMOS under conditions of low supply voltage and low threshold voltage still faces challenges in terms of stability. Therefore, Design Technology Co-Optimization (DTCO) is needed to simultaneously enhance performance and stability. This thesis considers experimental current-voltage data of low-temperature silicon FinFET, calibrated against TCAD models. It analyzes the performance of 6T and 8T Static Random-Access Memory (SRAM) under low-temperature conditions, examining characteristics such as read and write stability and speed. Finally, it presents optimized designs for 6T and 8T SRAM at 77K.

The thesis analyzes and compares three optimized SRAM designs: 6T opt2, Opt 6N2P 8T, and Opt-LVR 4N4P 8T. Results demonstrate that Opt-LVR 4N4P 8T SRAM outperforms other memory designs in various aspects. Compared to 77K 6T LVT, Opt-LVR 4N4P 8T SRAM achieves a 540% improvement in read stability and a 78% improvement in write stability. In terms of read time (-40%) and energy consumption (-61%), it outperforms the 300K 6T Baseline SRAM. Despite the larger area of 77K Opt-LVR 4N4P 8T SRAM, this issue can be addressed using Monolithic 3D (M3D) stacking technology. In M3D stacking, the SRAM circuit composed of 4 N-type and 4 P-type components can achieve a 40% overall area reduction by stacking one layer of N-type components and one layer of P-type components, overcoming the problem of excessive area. Additionally, compared to the 300K 6T Baseline SRAM, Opt-LVR 4N4P 8T SRAM demonstrates significant speed gains (+45%) at the same power, and lower power consumption (-73%) at the same speed. Even at a reduced supply voltage of 0.45V, Opt-LVR 4N4P 8T SRAM maintains good speed performance and reduces power consumption by 73%, making it highly suitable for high-performance computing applications.