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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 林宗賢 | zh_TW |
| dc.contributor.advisor | Tsung-Hsien Lin | en |
| dc.contributor.author | 毛瑋廣 | zh_TW |
| dc.contributor.author | Wei-Guang Mao | en |
| dc.date.accessioned | 2023-12-12T16:13:57Z | - |
| dc.date.available | 2023-12-13 | - |
| dc.date.copyright | 2023-12-12 | - |
| dc.date.issued | 2023 | - |
| dc.date.submitted | 2023-11-24 | - |
| dc.identifier.citation | [1] X. Gao, et al., "A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by N2," IEEE JSSC, vol. 44, no. 12,pp. 3253-3263, Dec. 2009.
[2] J. Zhu, et al., "A 0.0021 mm2 1.82mW 2.2GHz PLL Using Time-based Integral Control in 65nm CMOS," ISSCC, pp. 338-340, Feb. 2016. [3] B. Drost, M. Talegaonkar, and P. K. Hanumolu, “Analog filter design using ring oscillator integrators,” IEEE J. Solid-State Circuits, vol. 47, no. 12, pp. 3120–3129, Dec. 2012. [4] J. Chuang and H. Krishnaswamy, "A 0.0049mm2 2.3GHz sub-sampling ring-oscillator PLL with time-based loop filter achieving −236.2dB jitter-FOM," 2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017. [5] G. Su and S. Liu, "A 1.22 mW 2.4 GHz PLL Using a Single-Ring-Oscillator-Based Integrator With Background Frequency Calibration," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 7, pp. 2169-2179, July 2020. [6] P.-Y. Wang, S.-P. Chen, and P. Chen, “Timing orthogonal capacitance multiplication technique for PLL,” in Proc. IEEE Symp. VLSI Circuits,Jun. 2007, pp. 162–163. [7] H. Roder, “Amplitude, phase, and frequency modulation,” Proc. Inst.Radio Eng., vol. 19, no. 12, pp. 2145–2176, Dec. 1931. [8] X. Gao, E. A. M. Klumperink, G. Socci, M. Bohsali and B. Nauta, "Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector," in IEEE Journal of Solid-State Circuits, vol. 45, no. 9, pp. 1809-1821, Sept. 2010. [9] B. Razavi, "A study of injection locking and pulling in oscillators," in IEEE Journal of Solid-State Circuits, vol. 39, no. 9, pp. 1415-1424, Sept. 2004. [10] J. Lee and H. Wang, "Study of Subharmonically Injection-Locked PLLs," in IEEE Journal of Solid-State Circuits, vol. 44, no. 5, pp. 1539-1553, May 2009.. [11] A. Elkholy, M. Talegaonkar, T. Anand and P. Kumar Hanumolu, "Design and Analysis of Low-Power High-Frequency Robust Sub-Harmonic Injection-Locked Clock Multipliers," in IEEE Journal of Solid-State Circuits, vol. 50, no. 12, pp. 3160-3174, Dec. 2015. [12] Y. -C. Huang and S. -I. Liu, "A 2.4GHz sub-harmonically injection-locked PLL with self-calibrated injection timing," 2012 IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, 2012. [13] Sheng Ye, L. Jansson and I. Galton, "A multiple-crystal interface PLL with VCO realignment to reduce phase noise," in IEEE Journal of Solid-State Circuits, vol. 37, no. 12, pp. 1795-1803, Dec. 2002. [14] S. S. Nagam and P. R. Kinget, "A Low-Jitter Ring-Oscillator Phase-Locked Loop Using Feedforward Noise Cancellation With a Sub-Sampling Phase Detector," in IEEE Journal of Solid-State Circuits, vol. 53, no. 3, pp. 703-714, March 2018. [15] S. Choi, S. Yoo, Y. Lim and J. Choi, "A PVT-Robust and Low-Jitter Ring-VCO-Based Injection-Locked Clock Multiplier With a Continuous Frequency-Tracking Loop Using a Replica-Delay Cell and a Dual-Edge Phase Detector," in IEEE Journal of Solid-State Circuits, vol. 51, no. 8, pp. 1878-1889, Aug. 2016 [16] Pratap Tumkur Renukaswamy et al." Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation," in IEEE ISCAS 2021 [17] Soura Dasgupta et al,Systems & Control Letters, Volume 7, Issue 2,1986 [18] W. Wu et al., "A 28-nm 75-fsrms Analog Fractional-N Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction," in IEEE Journal of Solid-State Circuits, May 2019 [19] M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. A. M. Klumperink and B. Nauta, "A 10-bit Charge-Redistribution ADC Consuming 1.9uW at 1 MS/s," in IEEE Journal of Solid-State Circuits, vol. 45, no. 5, pp. 1007-1015, May 2010. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/91211 | - |
| dc.description.abstract | 本論文實現一個具有小面積之時間基底濾波器的次取樣鎖相迴路。
在這項研究中，我們達到突波以及抖動的降低。藉由使用改良的比例路徑、相位選擇技術及相位拉扯機制，降低了突波；此外，本架構亦採用背景相位噪音校正使得相位拉扯引起的噪音降低。此鎖相迴路採用TSMC 90奈米製程設計，運作於2.4 GHz、200 MHz的參考頻率，模擬的參考突波為-54 dBc，均方根抖動量為0.42 ps，功耗為7.8 mW，FoMJitter為-238.9 dB。 | zh_TW |
| dc.description.abstract | In this thesis, we present the implementation of a Sub-sampling PLL featuring a small area time-based loop filter. Within the confines of this study, we introduce a PLL achieving reduction in spurious signals and jitter. This reduction of the spur is made possible through the utilization of a modified proportional path, a phase selection technique, and a phase pulling mechanism. Furthermore, our implementation incorporates a background phase noise cancellation strategy, mitigating the noise-related consequences associated with the phase pulling process. The overall PLL is designed in TSMC 90-nm CMOS process. Operating at 2.4 GHz and 200 MHz reference frequency, the simulated reference spur level is -54 dBc, the integrated jitter is 0.42 ps with power consumption of 7.8 mW and the corresponding FoMJitter is -238.9 dB. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2023-12-12T16:13:57Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2023-12-12T16:13:57Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 論文口試委員審定書 i
摘要 iii Abstract iv List of Figures vii List of Tables x Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Overview 2 Chapter 2 Time-Based Integrator PLL 4 2.1 Introduction to Time-Based Integrator PLL Architectures 4 2.1.1 Divider-Based Time-Based Integrator PLL with Pseudo Differential CCROs 5 2.1.2 Sub-sampling Time-based Integrator PLL with Pseudo Differential CCROs 6 2.1.3 Time-Based Integrator PLL with Single CCRO and Frequency Compensation 7 2.1.4 Comparison Summary 8 2.2 Problems that Time-Based Integrator PLLs might Face 9 2.2.1 Multi-CCROs in One PLL 9 2.2.2 Spurious Tones due to Integrator CCRO(CCROI)’s Frequency Offset 9 2.2.3 Spurious Tones Caused by PWM Signal 11 Chapter 3 Methods for Optimizing PLL Performance 12 3.1 Sub-sampling Technique 12 3.1.1 Operation Principle 12 3.2 Injection-Locked Technique 15 3.2.1 Operation Principle 15 3.3 Phase Noise Cancellation Technique 18 3.3.1 Operation Principle 18 Chapter 4 Implementation of Proposed Time-Based Integrator PLL 21 4.1 Proposed Technique 22 4.1.1 Injecting into Integrator RO 22 4.1.2 Phase Selection and Phase Pulling Technique 23 4.1.3 Modified Proportion Path 30 4.2 Problem Arises as Injecting into Integrator RO 32 4.2.1 Phase Domain Explanation and Phase Noise Simulation 32 4.2.2 An Intuitive Way to Explain the Problem 33 4.2.3 Phase Noise Simulation 34 4.3 To Reduce the Effect from Injection 34 4.3.1 Phase Noise Cancellation Technique 34 4.4 Background Phase Noise Cancellation 35 4.4.1 Sign-Sign LMS 35 4.4.2 Delay Calibration 36 4.4.3 Offset Calibration 37 4.4.4 Simulation of the VCDL Gain 38 4.5 Circuit Implementation 39 4.5.1 CCRO1&2 39 4.5.2 V2I Circuit 40 4.5.3 D2I Circuit 40 4.5.4 SSPD 41 4.5.5 Comparator 42 4.5.6 DTC 43 4.5.7 R-2R DAC 43 4.5.8 VCDL 44 Chapter 5 Layout and Simulation Results 45 5.1 Layout 45 5.2 Simulation Results 46 5.2.1 Transient Waveform 46 5.2.2 Output Spectrum 48 5.2.3 Phase Noise 49 5.2.4 Power Consumption 54 5.3 Summary 54 Chapter 6 Conclusions and Future Works 56 6.1 Conclusions 56 6.2 Future Works 56 References 58 | - |
| dc.language.iso | en | - |
| dc.subject | 背景相位噪音校正 | zh_TW |
| dc.subject | 時間基底濾波器 | zh_TW |
| dc.subject | 相位選擇 | zh_TW |
| dc.subject | 相位拉扯 | zh_TW |
| dc.subject | 時間基底濾波器 | zh_TW |
| dc.subject | 相位選擇 | zh_TW |
| dc.subject | 相位拉扯 | zh_TW |
| dc.subject | 背景相位噪音校正 | zh_TW |
| dc.subject | Time-based Loop Filter | en |
| dc.subject | Phase Selection | en |
| dc.subject | Phase Pulling | en |
| dc.subject | Background Phase Noise Cancellation | en |
| dc.subject | Time-based Loop Filter | en |
| dc.subject | Phase Selection | en |
| dc.subject | Phase Pulling | en |
| dc.subject | Background Phase Noise Cancellation | en |
| dc.title | 一個具有時間基底迴路濾波器及使用注入和背景噪音校正技術之次取樣鎖相迴路 | zh_TW |
| dc.title | A Sub-sampling PLL using Time-based Loop Filter with Injection and Background Phase Noise Cancellation | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 112-1 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 李泰成;曾英哲 | zh_TW |
| dc.contributor.oralexamcommittee | Tai-Cheng Lee;Ying-Che Tseng | en |
| dc.subject.keyword | 時間基底濾波器,相位選擇,相位拉扯,背景相位噪音校正, | zh_TW |
| dc.subject.keyword | Time-based Loop Filter,Phase Selection,Phase Pulling,Background Phase Noise Cancellation, | en |
| dc.relation.page | 60 | - |
| dc.identifier.doi | 10.6342/NTU202304367 | - |
| dc.rights.note | 同意授權(全球公開) | - |
| dc.date.accepted | 2023-11-24 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-112-1.pdf | 3.34 MB | Adobe PDF | 檢視/開啟 |
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