二維/三維異質接面穿隧場效電晶體的製作

Abstract

隨著元件持續微縮，電源電壓與臨界電壓由於次臨界擺幅的熱限制而無法隨之降低，使積體電路的功耗問題愈發嚴峻，為了在室溫下實現次臨界擺幅低於60 mV/dec 的陡峭開關特性，穿隧電晶體因其與超大型積體電路製程的相容性與較低的關閉電流而備受期待，且二維結構的能態密度為階躍函數，二維/三維異質結構被預期能實現比三維結構更陡峭的開關。在本論文中，鍺/二硫化鉬異質接面穿隧電晶體在室溫下具有311 mV/dec 的最低次臨界擺幅，在過驅電壓為2 伏特時具有10^4的開關比；而鍺/二硫化錫異質接面閘極控制二極體則展示了負微分電阻的特性，其峰對谷電流比在-2 伏特的閘極電壓下可達到4.69。 為了實現二維/三維異質接面的對準與堆疊，我們設計並組裝了一套二維材料乾式轉移系統，而透過比較二維材料在光學顯微鏡下的顏色與原子力顯微鏡的厚度掃描結果，二維薄膜在具有100 奈米二氧化矽薄膜的矽基板上顏色對比度與厚度的關係被建立，使二維薄膜的厚度可以透過光學顯微鏡粗略地判定。此外，透過二維材料乾式轉移系統製作的預圖型背閘極二硫化鉬場效電晶體展現了155 mV/dec 的次臨界擺幅與在過驅電壓為2 伏特下具有10^7的開關比。鍺/二硫化鉬穿隧電晶體在常溫下能夠在過驅電壓為2 伏特時達到開關比10^4以及最低次臨界擺幅311 mV/dec，不同閘極氧化層厚度的鍺/二硫化鉬異質接面穿隧電晶體的量測結果確認了縮小閘極氧化層厚度可以有效降低元件的次臨界擺幅，然而氧化層與二維材料間的不完美界面可能是導致次臨界擺幅無法進一步下降的主因。p 型鍺的摻雜濃度也會影響鍺/二硫化鉬異質接面的穿隧機率，進而影響元件表現。鍺/二硫化鉬異質接面穿隧電晶體的變溫量測發現次臨界擺幅不受到溫度的影響，因此主要導通機制應不是熱傳輸，然而，元件中的導通機制是否為帶對帶穿隧效應仍需要進一步的研究與驗證。最後，對二維/三維異質接面穿隧電晶體的TCAD 模擬則展示了降低二維薄膜與閘極氧化層的厚度是優化元件表現的關鍵。

Power consumption becomes a great challenge as transistors are further scaled down since the threshold voltage cannot be reduced due to the limited subthreshold swing (SS) by Boltzmann transport. To achieve steep switching characteristics with SS of sub-60 mV/decade at room temperature, tunnel field-effect transistors (TFETs) are promising owing to their VLSI compatibility and low OFF current. Compared to 3D structures, 2D/3D heterojunction TFETs are expected to have steeper switching because the density of state in 2D structures is a step function. In this work, Ge/MoS2 heterojunction TFETs were fabricated, showing an ON/OFF ratio of 10^4 under an overdrive voltage of 2 V and an SS of 311 mV/decade at room temperature. A Ge/SnS2 gated diode with negative differential resistance (NDR) and a peak-to-valley current ratio (PVCR) of 4.69 is demonstrated. To achieve precise alignment and stacking of 2D/3D heterojunctions, a dry transfer system for 2D materials is built. By comparing the color of 2D films by optical microscope and the thickness by atomic force microscope on 100-nm SiO2/Si substrates, the color-thickness relationship of 2D films is established. Pre-patterned bottom-gated MoS2 FETs fabricated by the dry transfer system show the best SS of 155 mV/decade and an ON/OFF ratio of 10^7 under an overdrive voltage of 2 V. Ge/MoS2 heterojunction TFETs with an ON/OFF ratio of 10^4 under an overdrive voltage of 2 V and a minimum SS of 311 mV/dec are demonstrated. The results of Ge/MoS2 heterojunction TFETs with different gate oxide thicknesses confirm that reducing oxide thickness can improve the SS. However, the imperfect interface between the gate oxide and 2D films might be the limiting factor for further reduction of SS. The doping level of the p-Ge layer also affects the device performance due to the modulated tunneling probabilities at the Ge/MoS2 heterojunctions. The results of temperature-dependent measurement of Ge/MoS2 heterojunction TFETs show that SS does not change with temperature, which suggests that the dominant transport mechanism is not Boltzmann transport. However, whether the transport in those devices is dominated by the BTBT requires further investigation. Finally, TCAD simulations of 2D/3D heterojunction TFETs are performed and the results suggest that reducing the thickness of 2D films and gate oxide are key factors for further improvement of the device performance.