請用此 Handle URI 來引用此文件：
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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 劉致為 | zh_TW |
| dc.contributor.advisor | Chee Wee Liu | en |
| dc.contributor.author | 禹東秀 | zh_TW |
| dc.contributor.author | Dong Soo Woo | en |
| dc.date.accessioned | 2023-10-03T17:07:31Z | - |
| dc.date.available | 2023-11-09 | - |
| dc.date.copyright | 2023-10-03 | - |
| dc.date.issued | 2023 | - |
| dc.date.submitted | 2023-08-07 | - |
| dc.identifier.citation | [1] G. E. Moore, “Cramming more components onto integrated circuits,” Electronics, vol. 38, pp. 114-117, 1965.
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Liu, "Optical Detection of Parasitic Channels of Vertically Stacked Ge0.98Si0.02 nGAAFETs," in IEEE Transactions on Electron Devices, vol. 67, no. 10, pp. 4073-4078, Oct. 2020, doi: 10.1109/TED.2020.3016623. [25] H. -Y. Ye and C. W. Liu, " On-Current Enhancement in TreeFET by Combining Vertically Stacked Nanosheets and Interbridges," in IEEE Electron Device Letters, vol. 41, no. 9, pp. 1292-1295, Sept. 2020, doi: 10.1109/LED.2020.3010240. [26] Johnson, F.S., Miles, D.S., Grider, D.T. et al. Selective chemical etching of polycrystalline SiGe alloys with respect to Si and SiO2 . J. Electron. Mater. 21, 805–810 (1992). https://doi.org/10.1007/BF02665519 [27] Sun, Shiyu, et al. " Surface termination and roughness of Ge (100) cleaned by HF and HCl solutions." Applied Physics Letters 88.2 (2006): 021903. [28] Lee, T-E., et al. "Improvement of SiGe MOS interface properties with a wide range of Ge contents by using TiN/Y 2 O 3 gate stacks with TMA nassivation." 2019 Symposium on VLSI Technology. IEEE, 2019. [29] Y. -S. Huang et al., "High-Mobility CVD-Grown Ge/Strained Ge0.9Sn0.1/Ge Quantum-Well pMOSFETs on Si by Optimizing Ge Cap Thickness," in IEEE Transactions on Electron Devices, vol. 64, no. 6, pp. 2498-2504, June 2017, doi: 10.1109/TED.2017.2695664. [30] Bloem, J., and J. C. Van Vessem. "Etching Ge with Mixtures of HF‐H 2 O 2‐H 2 O." Journal of the electrochemical society 109.1 (1962): 33. [31] Kim, Joo-Hyung, et al. "Physical and electrical characterization of high-k ZrO2 metal–insulator–metal capacitor." Thin Solid Films 516.23 (2008): 8333-8336. [32] I. -H. Wong, Y. -T. Chen, J. -Y. Yan, H. -J. Ciou, Y. -S. Chen and C. W. Liu, "Fabrication and Low Temperature Characterization of Ge (110) and (100) p-MOSFETs," in IEEE Transactions on Electron Devices, vol. 61, no. 6, pp. 2215-2219, June 2014, doi: 10.1109/TED.2014.2318083. [33] H. Wu, W. Wu, M. Si and P. D. Ye, "Demonstration of Ge Nanowire CMOS Devices and Circuits for Ultimate Scaling," in IEEE Transactions on Electron Devices, vol. 63, no. 8, pp. 3049-3057, Aug. 2016, doi: 10.1109/TED.2016.2581862. [34] Genquan Han et al., "High-mobility germanium-tin (GeSn) P-channel MOSFETs featuring metallic source/drain and sub-370 °C process modules," 2011 International Electron Devices Meeting, Washington, DC, USA, 2011, pp. 16.7.1-16.7.3, doi: 10.1109/IEDM.2011.6131569. [35] M. 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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/90673 | - |
| dc.description.abstract | 隨著摩爾定律引領元件尺寸微小化，應變工程、高-k 值材料、以及FinFET元件結構被發明以及對此技術趨勢有貢獻。然而，3奈米以下電晶體必要新技術的應用為在有限的面積上提高元件效能。因此，對短通道效應控制性能高以及通道面積大的閘極環繞式電晶體(Gate-All-Around FET)結構會取代FinFET。
我們利用高遷移率材料，鍺矽(GeSi)，來製作比原本奈米片通道(Nanosheet)面積高的樹狀電晶體。樹狀電晶體控制H2O2濕蝕刻(wet etching)與磊晶層矽含量來形成個奈米片之間的橋樑(interbridge)區域。此區域和{111}/<110>與{110}/<110>表面，因此，提高元件通道面積，並提升驅動電流。我們利用化學沉積法長的高品質鍺矽磊晶層當奈米片與橋樑通道，Fin Formation和channel Release製程形成通道，通過PEALD與PVD製作Gate Stack。然後，利用黃光製程，PVD，Annealing製程製作S/D metal contact及做出完整的元件。 為獲得更大面積的{111}和{110}側面通道，我們設計不同GeSi磊晶層。我們利用三種奈米片結構Ge0.85Si0.15、 Ge0.9Si0.1 和Ge0.97Si0.03/Ge0.9Si0.1/Ge0.97Si0.03, 並用兩種橋樑結構n+ Ge/Ge0.95Si0.05/Ge與n+ Ge。結果，利用 Ge0.9Si0.1奈米片與n+ Ge IB通道的元件表示 SS=104mV/dec 與ION/IOFF~4E3 在VDS=0.05V，並表示 ION=26μA和ID per footprint =154 μA/ μm 在VOV=VDS=0.5V。然後利用Ge0.97Si0.03/Ge0.9Si0.1/Ge0.97Si0.03奈米片和n+ Ge IB通道的元件表示SS=111mV/dec 與ION/IOFF~2.1E3 在VDS=0.05V，並表示 ION=20μA和ID per footprint =111 μA/ μm 在VOV=VDS=0.5V。 我們也利用另高遷移率材料鍺錫(GeSn) 製作4根堆疊奈米片電晶體。此元件通過乾蝕刻(Dry Etching)形成通道均勻性高的元件。我們製作兩種不同厚度的GeSn(10%) 通道與GeSn(5%)以及Ge/GeSn(5%)蓋層。因Ge或GeSn(5%) 蓋層有量子阱效應分離Ge/Oxide 介面層的載子，並降低通道裡的雜質散射(Impurity Scattering)與表面粗糙度散射(Surface Roughness Scattering)。 我們通過製程和實驗發現厚GeSn(10%)通道和薄Ge/GeSn(5%)蓋層具有ION=924 μA/ μm 在VOV=VDS=0.5V。然而，薄GeSn(10%)通道和厚GeSn(5%) 蓋層提供ION=503 μA/ μm 在VOV=VDS=0.5V。通過試驗，展示了利用調整磊晶層厚度的方式可提高元件的效能。 | zh_TW |
| dc.description.abstract | As Moore’s Law has led the continuous scaling of devices, strain engineering, high-k material, and FinFET architecture have been invented and contributed to the technology trends. Furthermore, further innovations such as high NA EUV lithography, 2.5D and 3D advanced packaging, and 3D transistor architecture have been invented for next generation transistors. Among these new technologies, Gate-All-Around Field Effect-Transistor (GAAFET) is suggested as the most promising solution to replace traditional FinFET. Co-optimizing this new transistor architecture with high quality epitaxy design of new channel materials with strain effects, highly selective channel release, and PEALD-based high-k dielectric gate stack formation would provide high device performance improvement.
In this thesis, GeSi channel TreeFET process integration is going to be introduced. TreeFET architecture expands the effective channel width compared to the traditional nanosheet structure by utilizing the sacrificial layers in between nanosheets. By controlling channel release, sufficient interbridge regions can be obtained. The wet etching-based channel release can be controlled to achieve {111} and {110} surface orientations of the interbridges that provide higher mobilities than {100} surfaces. Furthermore, parasitic channel removal is also going to be conducted in wet etching using H2O2 and NH4OH, which can further reduce leakage current. For interbridge of highly stacked TreeFET, n+ Ge/Ge0.95Si0.05/Ge epi-structure might not provide ideal etching results due to difference in etching rate. Therefore, two other structures: Ge0.9Si0.1 channel with n+ Ge interbridge and Ge0.97Si0.03/Ge0.9Si0.1/Ge0.97Si0.03 channel with n+ Ge are going to be introduced and integrated with channel release and gate stack processes to compare performance difference. For Ge0.85Si¬0.15 channels with n+ Ge/Ge0.95Si0.05/Ge interbridge structure provides WNS=181~220nm, WIB=114~143nm, and SS=97mV/dec and ION/IOFF=2E3 at VDS=0.05V. The Ge0.9Si0.1 channel with n+ Ge interbridge structure results in WNS=171nm and SS=104mV/dec and ION/IOFF=4E3 at VDS=0.05V. Lastly, Ge0.97Si0.03/Ge0.9Si0.1/Ge0.97Si0.03 channel with n+ Ge interbridge structure obtain WNS=178nm and SS=111mV/dec and ION/IOFF=2.1E3 at VDS=0.05V. Further comparisons are going to be addressed throughout the chapters. Process integration of GeSn nanosheet with capping layers FET is going to be introduced. The chapter introduces performance differences resulted by different thicknesses of GeSn channel and cap structures. Thick Ge¬Sn(10%) channel sandwiched between thin Ge/GeSn(5%) caps and thin GeSn(10%) channel located between thick GeSn(5%) caps are going to fabricated and compared. Highly selective isotropic dry etching is going to be used for channel release to achieve high etching selectivity and uniformity of each channel. And PEALD gate stack formation is going to be integrated for GAA property. As a result, thick Ge¬Sn(10%) channel combined with thin Ge/GeSn(5%) caps formation provides SS=126mV/dec and IONIOFF=6.4E3 at VDS=-0.05V. And, thin GeSn(10%) channel combined with thick GeSn(5%) caps formation provides SS=101mV/dec and ION/IOFF=11.3E3 at VDS=-0.05V. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2023-10-03T17:07:31Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2023-10-03T17:07:31Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | Table of Contents
Publication List (相關論文發表) i 摘要 ii Abstract iv Table of Contents vii List of Figures ix Chapter 1 1 1.1 Background and Motivation 1 1.2 Organization 5 Chapter 2 7 Channel Release for Highly Stacked GeSi TreeFETs 7 2.1 Introduction 7 2.2 Epitaxial Layer of GeSi TreeFET 8 2.3 Channel Release for GeSi TreeFET 11 2.4 Parasitic Channel Control 14 2.5 Summary 16 Chapter 3 17 Integration of Highly Stacked GeSi TreeFET 17 3.1 Introduction 17 3.2 TreeFET Channel Optimization 18 3.3 Device Integration 19 3.4 Electrical Characteristics and Device Analysis 24 3.5 Summary 30 Chapter 4 32 Integration of 4 Stacked GeSn Nanosheet Field-Effect Transistor 32 4.1 Introduction 32 4.2 GeSn Channel Epilayer Design 33 4.3 Channel Release of 4 Stacked GeSn Channels 36 4.4 Gate Stack Formation 39 4.5 Device Analysis 41 4.6 Summary 47 Chapter 5 49 Summary and Future Work 49 5.1 Summary 49 5.2 Future work 50 Reference 52 | - |
| dc.language.iso | en | - |
| dc.subject | 鍺錫 | zh_TW |
| dc.subject | 樹狀電晶體 | zh_TW |
| dc.subject | 鍺矽 | zh_TW |
| dc.subject | 奈米片 | zh_TW |
| dc.subject | 橋樑 | zh_TW |
| dc.subject | Germanium-Silicon | en |
| dc.subject | TreeFET | en |
| dc.subject | Nanosheet | en |
| dc.subject | Germanium-Tin | en |
| dc.subject | Interbridge | en |
| dc.title | 通道堆疊鍺錫閘極環繞式電晶體及鍺矽樹狀電晶體結合奈米片及橋樑之製程整合 | zh_TW |
| dc.title | Integration of Stacked GeSn GAAFETs and GeSi TreeFETs Combining Nanosheets and Interbridges | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 111-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 廖洺漢 ;李敏鴻;林楚軒;林中一 | zh_TW |
| dc.contributor.oralexamcommittee | Ming Han Liao;Min-Hung Lee;Chu-Hsuan Lin;Chung-Yi Lin | en |
| dc.subject.keyword | 鍺錫,鍺矽,樹狀電晶體,奈米片,橋樑, | zh_TW |
| dc.subject.keyword | Germanium-Tin,Germanium-Silicon,TreeFET,Nanosheet,Interbridge, | en |
| dc.relation.page | 61 | - |
| dc.identifier.doi | 10.6342/NTU202303060 | - |
| dc.rights.note | 同意授權(限校園內公開) | - |
| dc.date.accepted | 2023-08-09 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| dc.date.embargo-lift | 2026-08-06 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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