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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/89953完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳景然 | zh_TW |
| dc.contributor.advisor | Ching-Jan Chen | en |
| dc.contributor.author | 許博彥 | zh_TW |
| dc.contributor.author | Bo-Yan Xu | en |
| dc.date.accessioned | 2023-09-22T16:48:56Z | - |
| dc.date.available | 2023-11-09 | - |
| dc.date.copyright | 2023-09-22 | - |
| dc.date.issued | 2023 | - |
| dc.date.submitted | 2023-08-09 | - |
| dc.identifier.citation | [1] F. C. Lee, “Power supplies trends – from architecture to building blocks,” presented at National Semiconductor Virtual Laboratories Distinguished Faculty Seminar, 2010. Available at http://www.cpes.vt.edu.
[2] B. Lee, M. K. Song, A. Maity, D. Brian M, “10.7 A 25MHz 4-phase SAW hysteretic DC-DC converter with 1-cycle APC achieving 190ns tsettle to 4A load transient and above 80% efficiency in 96.7% of the power range,” in IEEE ISSCC, Mar. 2017. [3] C. Song, “Accuracy analysis of constant-on time current-mode dc-dc converters for powering microprocessors,” in Proc. IEEE APEC, 2009, pp. 97-101. [4] R. Redl and J. Sun, “Ripple-based control of switching regulators – An overview,” IEEE Trans. Power Electron., vol.24, no. 12, pp. 2669-2280, Dec. 2009. [5] J. Sun, “Characterization and performance comparison of ripple based control for voltage regulators modules,” IEEE Trans. Power Electron., vol.21, no. 2, pp. 346-353, Mar. 2006. [6] J. Li and F. C. Lee, “Modeling of V2 current-mode control,” in Proc. IEEE APEC, 2009, pp. 298-304. [7] S. Qu, “Modeling and design considerations of V2 controlled buck regulator,” in Proc. IEEE APEC, 2001, pp. 507-513. [8] Y.-J. Chen, D. Chen, Y.-C. Lin, and C.-J. Chen “A novel constant on-time current-mode control scheme to achieve adaptive voltage positioning for DC power converters,” in Proc. IEEE IECON 2012, pp. 104-109. [9] K. Yao, Y. Ren, J. Sun, K. Lee, M. Xu, J. Zhou and F. C, Lee, “Adaptive voltage position design for voltage regulators,” in Proc. IEEE APEC, 2004, pp. 272-278. [10] C. Song and J. L. Nilles, “Multiple-phase high-accuracy hysteretic current-mode voltage regulator for powering micorprocessors,” in Proc. IEEE APEC, 2008, pp. 517-522. [11] W. Huang, D. Clavette, G. Schuellein, M. Crowther and J. Wallace, “System accuracy analysis of the multiphase voltage regulator module,” IEEE Trans. Power Electron., vol.22, no. 3, pp. 1019-1026, May 2007. [12] F. Yu, F. C. Lee, and P. Mattavelli “A small-signal model for V¬2 control with composite output capacitors based on describing function approach,” in Proc. IEEE ECCE, 2011, pp. 1236-1243. [13] Y. Lee, S. Wang, and K. Chen, “Quadratic differential and integration technique in V2 control buck converter with small ESR capacitors,” IEEE Trans. Power Electron., vol.25, no. 4, pp. 829-838, Apr. 2010. [14] C. C. Fang and R. Redl, “Subharmonic stability limits for the buck converter with ripple-based constant on-time control and feedback filter,” IEEE Trans. Power Electron., vol.29, no. 4, pp. 2135-2142, Apr. 2013. [15] T. Qian and W. Wu, “Analysis of the ramp compensation approaches to improve stability for buck converters with constant-on-time control,” IET Power Electronics, vol.5, issue. 2, 2012, pp. 196-204. [16] T. Qian, “Subharmonic analysis for buck converters with constant.on-time control and ramp compensation,” IEEE Trans. Industrial Electron., vol. 60, no. 5, pp. 1780-1786, May, 2013. [17] S. Tian, F. C. Lee, Q. Li and Y. Yan, “Unified equivalent circuit model of V2 control,” in Proc. IEEE APEC, 2014, pp. 1016-1023. [18] M. Lee, D. Chen, K. Huang, C. W. Liu and B. Tai, “Modeling and design for a novel adaptive voltage positioning (AVP) scheme for multiphase VRMs,” IEEE Trans. Power Electron., vol. 23, no. 4, pp. 1733-1742, Jul. 2008. [19] C. Chen, D. Chen, C. Tseng, Y. Chang and K. Wang, “A novel ripple-based constant on-time control with virtual inductor current ripple for buck converter with ceramic output capacitors,” in Proc. IEEE APEC, 2011, pp. 1488-1493. [20] Y. C. Lin, C. J. Chen, D. Chen, B. Wang, “A ripple-based constant on-time control with virtual inductor current and offset cancellation for DC power converter,” IEEE Trans. Power Electron., Vol. 27, no. 10, pp 4301-4310, Oct. 2012. [21] S. Tian, F. C. Lee, P. Mattavelli, K.-Y. Cheng and Y. Yan, “Small-Signal Analysis and Optimal Design of External Ramp for Constant On-Time V2 Control with Multilayer Ceramic Caps,” IEEE Trans. Power Electron., vol. 29, no. 8, pp. 4450-4460, Aug. 2014. [22] Y. Yan, F. C. Lee, S. Tian and P.-H. Liu, “Modeling and Design Optimization of Capacitor Current Ramp Compensated Constant On-Time V2 Control,” IEEE Trans. Power Electron., vol. 33, no. 8, pp. 7288-7296, Aug. 2018. [23] H. K. Krishnamurthy et al., “20.1 A digitally controlled fully integrated voltage regulator with on-die solenoid inductor with planar magnetic core in 14nm tri-gate CMOS,” in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC), 2017. [24] Minho Choi, Chan-Ho Kye, Jonghyun Oh, Min-Seong Choo, Deog-Kyoon Jeong, “A synthesizable digital AOT 4-phase buck voltage regulator for digital systems with 0.0054mm2 controller and 80ns recovery time,” in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC), 2019. [25] S. Kapat and P. T. Krein, “Improved time optimal control of a buck converter based on capacitor current,” IEEE Trans. Power Electron., Vol. 27, no. 3, pp. 1444–1454, Mar. 2012. [26] S. H. Chien, T. H. Hung, S. Y. Huang, T.-H. Kuo, “A monolithic capacitor-current-controlled hysteretic buck converter with time-optimized feedback circuit,” IEEE J. Solid-State Circuits, Vol. 50, no. 11, pp.2524-2532, Nov. 2015. [27] S.-Y. Huang, K.-Y. Fang, Y.-W. Huang, S.-H. Chien, T.-H. Kuo, “Capacitor-current-sensor calibration technique and application in a 4-Phase buck converter with load-time optimization,” in IEEE ISSCC, Feb. 2016, pp.228-229. [28] Y. W. Huang, T.-H. Kuo, S. Y. Huang, and K. Y. Fang, “A Four-Phase Buck Converter With Capacitor-current–sensor Calibration for Load-Time-Response Optimization That Reduces Undershoot/Overshoot and Shortens Settling Time to Near Their Theoretical Limits,” IEEE J. Solid-State Circuits, Vol. 53, no. 2, pp. 552-568, Feb. 2018. [29] G. Feng, E. Meyer, Y.-F. Liu, “A New Digital Control Algorithm to Achieve Optimal Dynamic Performance in DC-to-DC Converters,” IEEE Trans. Power Electron., Vol. 22, no. 4, pp.1489-1498, Jul. 2007. [30] E. Meyer, Z. Zhang, Y.-F. Liu, “An optimal control method for buck converters using a practical capacitor charge balance technique,” IEEE Trans. Power Electron., Vol. 23, no. 4, pp.1802-1812, Jul. 2008 [31] S. C. Huerta, P. Alou, J. A. Oliver, O. Garcia, J. A. Cobos, and A. Abou-Alfotouh, “Design methodology of a non-invasive sensor to measure the current of output capacitor for a very fast non-linear control,” in Proc. IEEE Appl. Power Electron. Conf., 2009, pp. 806-811. [32] S. C. Huerta, P. Alou, J. A. Oliver, O. Garcia, J. A. Cobos, and A. Abou-Alfotouh, “Non-linear control for DC-DC converters based on hysteresis of the COUT current with a frequency loop to operate at constant frequency,” IEEE Trans. Industrial Electron., Vol. 58, no. 3, pp. 1036–1043, Mar. 2011. [33] S. C. Huerta, A. Soto, P. Alou, J. A. Oliver, O. Garcia, J. A. Cobos, “Advanced Control for Very Fast DC-DC Converters Based on Hysteresis of the Cout Current,” IEEE Trans. on Circuits and Systems, Vol. 60, no. 4, Apr 2013. [34] M. Bazes, “Two novel fully complementary self-biased CMOS differential amplifiers,” IEEE J. Solid-State Circuits, Vol. 26, no. 2, pp. 165-168, Feb. 1991. [35] RD0004 datasheet, “Richtek Load Transient Tool User Manual,” Dec. 2016, Available on http://www.richtek.com. [36] Y.-C. Li, C.-J. Chen, C.-J. Tsai, “A Constant On-Time Buck Converter with Analog Time-Optimized On-time Control,” IEEE Transactions on Power Electronics, vol. 35, no. 4, pp. 3754-3765, Apr. 2020 [37] Angel V. Peterchev Seth R. Sanders., “Quantization Resolution and Limit Cycling in Digitally Controlled PWM Converters” in 2001 IEEE 32nd Annual Power Electronics Specialists Conference [38] Minho Choi, Chan-Ho Kye, Jonghyun Oh, Min-Seong Choo, Deog-Kyoon Jeong, “A Current-Mode Digital AOT 4-Phase Buck Voltage Regulator” in IEEE Solid-State Circuits Letters, vol. 2, no. 11, Nov. 2019 [39] Kent Yancik, ON Semiconductor Analog Power Group, “CPU power control: Compare single-edge, dual-edge controller architectures” Nov. 2006,available on https://www.eetimes.com/cpu-power-control-compare-single-edge-dual-edge-controller-architectures/ [40] D. -H. Jung, K. Kim, S. Joo, and S.-O. Jung, “0.293-mm2 fast transient response hysteretic quasi-V2 DC-DC Converter with area-efficient time-domain-based controller in 0.35-μm CMOS,” IEEE J. Solid-State Circuits, Vol.53, no. 6, pp.1844-1855, Jun. 2018. [41] K.-I Wu, B.-T Hwang, and C.C-P. Chen, “Synchronous double-pumping technique for integrated current-mode PWM DC-DC converters demand on fast-transient response,” IEEE Trans. Power Electron., Vol. 32, no. 1, pp. 849-865, Jan. 2017. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/89953 | - |
| dc.description.abstract | 隨著製程的進步，由於大多數先進製程主要是以提供數位晶片(digital ICs)的前提下進行開發設計的，因此許多電路設計工程師嘗試將電路的功能盡可能地數位化，以利承載著先進製程的好處。因此，本篇論文提出了一個具數位控制漣波注入及數位暫態時間最佳化控制之混合型控制降壓轉換器，所提出的混合型控制器有著漣波控制的基本架構，還有著電壓模式的高頻寬補償迴路設計，所提出的控制操作可以分為三個路徑: (1)數位控制漣波注入的路徑增強了基於漣波控制的穩定性，並感測出有分正負號的輸出電壓與基準電壓的差距("ERROR")給補償器進行導通時間的調變。(2)本架構之慢迴路補償路徑是一個與快迴路相比相對較慢的路徑，負責嚴格調節輸出電壓。此外，有著基於漣波控制架構的特性，關閉時間也會被調整。與其他只能控制上述之一的數位控制器相比，本架構可以更加準確地輸出各種負載條件下須對應到的佔空比，以抑制極限循環震盪的發生。(3)快迴路為數位暫態時間最佳化控制路徑，負責快速的動態響應，以在大迴轉率(Slew Rate)的抽載/卸載下實現最快的暫態響應。
本論文所提出的控制架構與功率級電晶體(PowerMos)採用台積電 0.18-µm CMOS混訊製程(Mixed-Signal Process)實現。量測波形顯示，在輸出電容為2µF，輸出電壓為1.0V以迴轉率1A/1µs變化下進行抽載，本架構之慢迴路補償路徑能在590ns使輸出電壓回穩，暫態的掉落電壓為53.3mV，另一方面在迴轉率為1A/500ns變化下進行卸載，能提供在809ns使輸出電壓回穩，暫態的上升電壓為66.6mV;另外，相比於慢迴路補償路徑，量測波形也顯示了當使用數位暫態時間最佳化控制時，在上述同樣的負載變化環境下，則減少了抽載時所造成的輸出掉落電壓51%，而卸載時減少了輸出突波電壓46.7%，且輸出電壓回穩的時間也皆有相當的改善。 | zh_TW |
| dc.description.abstract | With the progress of the process, because most advanced processes are mainly designed on the premise of providing digital ICs, many circuit design engineers try to digitalize the circuit function as much as possible in order to carry the benefits of advanced processes. Therefore, a hybrid controlled buck converter with digitally controlled ripple injection and digital time-optimized control is proposed in this thesis. The proposed hybrid controller has a basic architecture of ripple-based control and a high-bandwidth compensation loop design in voltage-mode control. The proposed control operation can be divided into three paths. (1) The digitally controlled ripple-injection path enhances the stability of ripple-based control, and sense the signed "ERROR" between the output voltage and the reference voltage to the compensator for on-time adaptation. (2) The slow-loop compensation path is a relatively slow path compared to the fast loop, which is responsible to regulate tightly the output voltage. Besides, with the characteristics of ripple-based controlled architecture, the off-time will also be adjusted. Compared with the other digital controller which can only control one of the above, it can more accurately output the corresponding duty ratio for various load conditions as much as possible to suppress the occurrence of limit cycle oscillations (3) The fast loop is digital time-optimized control (TOC) path, which is responsible for fast dynamic response to achieve the fastest transient response under the large slew-rate load step-up/step-down transient.
The control architecture and PowerMos proposed in this thesis are fabricated by TSMC 0.18-µm CMOS Mixed-Signal Process. The measurement result shows that when the output capacitor is 2µF, the output voltage is specified by 1.0V, and load step-up transient with a slew rate of 1A/1µs, the slow-loop compensation path can stabilize the output voltage within 590ns. The undershoot voltage during the transient state is 53.3mV. On the other hand, when load step-down transient with a slew rate of 1A/500ns, it is capable of stabilizing the output voltage within 809ns. The overshoot voltage during the transient state is 66.6mV. In addition, in the same load variation environment mentioned above, compared with the slow-loop compensation path, the measurement result shows that when using digital time-optimized control, it reduces the undershoot voltage caused by load step-up transient by 51%, and reduces the overshoot voltage caused by load step-down transient by 46.7%. Furthermore, the settling time of the output voltage is also significantly improved in both cases. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2023-09-22T16:48:56Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2023-09-22T16:48:56Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 口試委員審定書 i
致謝 ii 摘要 iii Abstract iv Contents vi List of Figures ix List of Tables xvi Chapter 1 Introduction 1 1.1 Background: Voltage Regulators (VRs) for Microprocessors, Memory and Low Supply Voltage Applications 1 1.2 Introduction of Voltage-Mode Control Operation for Buck Converter and Digitally Controlled Circuit Trend 5 1.2.1 Traditional Voltage-Mode Control 5 1.2.2 Digitally Controlled Voltage-Mode Control 7 1.2.3 The Issue of Limit Cycle Oscillation 10 1.3 Introduction of Constant On-Time Control Operation for Buck Converter 13 1.3.1 Conventional Constant On-Time Control 13 1.3.2 Stability Analysis of Ripple-Based Constant On-Time (RBCOT) Control 16 1.3.3 Techniques to Solve Unstable Issue of RBCOT Control with Ramp Compensation 18 1.4 Thesis Motivation 22 1.5 Thesis Outline 26 Chapter 2 Review of Digital Control and Hybrid Control for Buck Converter 28 2.1 Digital Controlled Voltage-Mode Structure 28 2.2 Digital Ripple-Injection Scheme Structure 32 2.3 Buck Converter with Time-Optimized Control 38 Chapter 3 The Proposed Control Schemes for Buck Converter 42 3.1 Block Diagram of the Architecture with the Proposed Control 42 3.2 Digitally Controlled Ripple Injection to Achieve Pseudo-Constant Switching Frequency Control 44 3.3 Digital Time-Optimized Control 52 3.4 Digital Dither Control Mechanism 57 3.5 Summary 62 3.5.1 Contribution differences from previous work 62 3.5.2 Switching frequency variation and design considerations 64 Chapter 4 Circuit Implementation 73 4.1 Implementation of Digitally Controlled Ripple Injection to Achieve Pseudo-Constant Switching Frequency Control 73 4.1.1 Digitally Controlled Ripple-Injection Waveform Generator Design 73 4.1.2 Digital Proportional-Integral-Derivative (PID) Compensator Design 76 4.2 Non-Invasive Cap-Current Sensor Design 84 4.3 Implementation of Digital Time-Optimized Control 90 Chapter 5 Simulation and Measurement Results 102 5.1 Introduction 102 5.2 Printed Circuit Board (PCB) Design and Measurement Setup 107 5.3 Simulation and Measurement Results 111 Chapter 6 Conclusions and Future Works 124 6.1 Conclusions 124 6.2 Future Works 125 Reference 126 | - |
| dc.language.iso | en | - |
| dc.subject | 暫態時間最佳化控制 | zh_TW |
| dc.subject | 假定頻控制 | zh_TW |
| dc.subject | 可合成邏輯設計 | zh_TW |
| dc.subject | 導通時間調變 | zh_TW |
| dc.subject | 基於漣波控制 | zh_TW |
| dc.subject | 數位控制電壓調節器 | zh_TW |
| dc.subject | 降壓型轉換器 | zh_TW |
| dc.subject | 積體電路 | zh_TW |
| dc.subject | pseudo-constant switching frequency control | en |
| dc.subject | synthesizable logic design | en |
| dc.subject | integrated circuit (IC) | en |
| dc.subject | time-optimized control (TOC) | en |
| dc.subject | digitally controlled voltage regulator | en |
| dc.subject | on-time adaptation | en |
| dc.subject | ripple-based control | en |
| dc.subject | Buck converter | en |
| dc.title | 具數位控制漣波注入及數位暫態時間最佳化控制之混合型控制降壓轉換器 | zh_TW |
| dc.title | A Hybrid Controlled Buck Converter with Digitally Controlled Ripple Injection and Digital Time-Optimized Control | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 111-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 陳耀銘;蔡建泓 | zh_TW |
| dc.contributor.oralexamcommittee | Yaow-Ming Chen;Chien-Hung Tsai | en |
| dc.subject.keyword | 降壓型轉換器,數位控制電壓調節器,基於漣波控制,導通時間調變,假定頻控制,暫態時間最佳化控制,積體電路,可合成邏輯設計, | zh_TW |
| dc.subject.keyword | Buck converter,digitally controlled voltage regulator,ripple-based control,on-time adaptation,pseudo-constant switching frequency control,time-optimized control (TOC),integrated circuit (IC),synthesizable logic design, | en |
| dc.relation.page | 130 | - |
| dc.identifier.doi | 10.6342/NTU202303867 | - |
| dc.rights.note | 同意授權(限校園內公開) | - |
| dc.date.accepted | 2023-08-11 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| dc.date.embargo-lift | 2028-08-09 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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