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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 李建模 | zh_TW |
dc.contributor.advisor | Chien-Mo Li | en |
dc.contributor.author | 謝秉翰 | zh_TW |
dc.contributor.author | Bing-Han Hsieh | en |
dc.date.accessioned | 2023-08-16T16:43:03Z | - |
dc.date.available | 2023-11-09 | - |
dc.date.copyright | 2023-08-16 | - |
dc.date.issued | 2023 | - |
dc.date.submitted | 2023-08-07 | - |
dc.identifier.citation | J. Mahmod, S. Millican, U. Guin, and V. Agrawal, “Special Session: Delay Fault Testing - Present and Future,” in VLSI Test Symposium, pp. 1–10, 2019.
P. Muthukrishnan and S. Sathasivam, “A Technical Survey on Delay Defects in Nanoscale Digital VLSI Circuits,” Applied Sciences, vol. 12, no. 18, 2022. Siemens EDA Software, Tessent Diagnosis User’s Manual, v2023.1, 2023. N. Ahmed, M. Tehranipoor, and V. Jayaram, “Timing-Based Delay Test for Screening Small Delay Defects,” in Design Automation Conference, p. 320–325, 2006. X. Lin, K.-h. Tsai, C. Wang, M. Kassab, J. Rajski, T. Kobayashi, R. Klingenberg, Y. Sato, S. Hamada, and T. Aikyo, “Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects,” in Asian Test Symposium, pp. 139–146, 2006. S. Tanwir, S. Prabhu, M. Hsiao, and L. Lingappan, “Information-theoretic and statistical methods of failure log selection for improved diagnosis,” in International Test Conference, pp. 1–10, 2015. R. Guo, W.-T. Cheng, T. Kobayashi, and K.-H. Tsai, “Diagnostic test generation for small delay defect diagnosis,” in International Symposium on VLSI Design, Automation and Test, pp. 224–227, 2010. C.-H. Wu, S. J. Lee, and K.-J. Lee, “Test and diagnosis pattern generation for dynamic bridging faults and transition delay faults,” in Asia and South Pacific Design Automation Conference, pp. 755–760, 2016. O. Poku and R. D. Blanton, “Delay defect diagnosis using segment network faults,” in International Test Conference, pp. 1–10, 2007. S. Kundu, G. Bhargava, L. Endrinal, and L. Ranganathan, “Using Custom Fault Models to Improve Understanding of Silicon Failures,” in International Test Conference, pp. 348–354, 2022. T. Yoneda, K. Hori, M. Inoue, and H. Fujiwara, “Faster-than-at-speed test for increased test quality and in-field reliability,” in International Test Conference, pp. 1–9, 2011. A. Krstic, L.-C. Wang, K.-T. Cheng, J.-J. Liou, and T. Mak, “Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models,” in Design Automation Conference, pp. 668–673, 2003. Z. Wang, M. Marek-Sadowska, K.-H. Tsai, and J. Rajski, “Delay fault diagnosis using timing information,” in International Symposium on Signals, Circuits and Systems, pp. 485–490, 2004. T. Aikyo, H. Takahashi, Y. Higami, J. Ootsu, K. Ono, and Y. Takamatsu, “TimingAware Diagnosis for Small Delay Defects,” in International Symposium on Defect and Fault-Tolerance in VLSI Systems, pp. 223–234, 2007. P.-J. Chen, W.-L. Hsu, J. C.-M. Li, N.-H. Tseng, K.-Y. Chen, W.-p. Changchien, and C. C. Liu, “An Accurate Timing-Aware Diagnosis Algorithm for Multiple Small Delay Defects,” in Asian Test Symposium, pp. 291–296, 2011. E. J. Jang, J. Chung, and J. A. Abraham, “Delay defect diagnosis methodology using path delay measurements,” in International Symposium on Integrated Circuits, pp. 317–320, 2011. A. M. Somashekar and S. Tragoudas, “Diagnosis of small delay defects arising due to manufacturing imperfections using path delay measurements,” in International Symposium on Quality Electronic Design, pp. 481–486, 2013. V. J. Mehta, M. Marek-Sadowska, K.-H. Tsai, and J. Rajski, “Timing-Aware Multiple-Delay-Fault Diagnosis,” in International Symposium on Quality Electronic Design, pp. 246–253, 2008. S. Holst, E. Schneider, M. A. Kochte, X. Wen, and H.-J. Wunderlich, “VariationAware Small Delay Fault Diagnosis on Compressed Test Responses,” in International Test Conference, pp. 1–10, 2019. V. J. Mehta, M. Marek-Sadowska, K.-h. Tsai, and J. Rajski, “Timing Defect Diagnosis in Presence of Crosstalk for Nanometer Technology,” in International Test Conference, pp. 1–10, 2006. L. Huisman, M. Kassab, and L. Pastel, “Data mining integrated circuit fails with fail commonalities,” in International Test Conference, pp. 661–668, 2004. C. Shan, P. Babighian, Y. Pan, J. Carulli, and L.-C. Wang, “Systematic defect detection methodology for volume diagnosis: A data mining perspective,” in International Test Conference, pp. 1–10, 2017. S. Wang and W. Wei, “Machine learning-based volume diagnosis,” in Design, Automation & Test in Europe Conference & Exhibition, pp. 902–905, 2009. M.-T. Wu, C.-S. Kuo, J. C.-M. Li, C. Nigh, and G. Bhargava, “Improving Volume Diagnosis and Debug with Test Failure Clustering and Reorganization,” in International Test Conference, pp. 251–259, 2021. | - |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/89001 | - |
dc.description.abstract | 由於技術節點的減小和操作頻率的增加,延遲故障在現代設計中變得越來越重要。然而,與時序相關的測試失敗通常只有很少的故障位,因此延遲故障的診斷是具有挑戰性的。本研究提出了一種兩階段流程,用於識別系統性延遲故障並提高相對應的診斷解析度。在第一階段,從延遲故障中觀察到大量測試失敗之間的子集關係。這些子集關係被進一步分析以識別系統性缺陷。在第二階段,選擇一組測試失敗作為代表性測試失敗,用於表示缺陷行為。這些代表性測試失敗被用來做進一步的診斷。將提出的技術實驗在一個工業設計晶片中,其中兩個核心上顯示具有三個系統性案例,透過所提出的技術,延遲故障診斷解析度分別提高了超過 33 倍、69 倍和 8 倍。此外,所提出的技術可以融合進現有容量診斷方法,並可在執行過程中與當前商業診斷工具進行整合。 | zh_TW |
dc.description.abstract | Delay faults have become increasingly important in modern designs due to decreasing technology node size and increasing operation frequency. However, diagnosis of delay faults can be challenging since there are typically few failing bits in the timing-related test failures. In this work, a two-phase flow is presented to identify systematic delay failures and improve their corresponding diagnosis resolution. In the first phase, a significant amount of subset relationships among test failures are observed for the delay failures. These subset relationships are further analyzed to identify systematic defects. In the second phase, a set of test failures are selected as representative test failures, which are used to represent the defect behavior. These representative test failures are further applied to diagnosis. Experiments on two cores of an industrial design with three systematic cases show over 33×, 69×, and 8× improvement on delay fault diagnosis resolution. Furthermore, the proposed technique can integrate with existing volume diagnosis methodologies, and incorporates current commercial diagnosis tools in its execution. | en |
dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2023-08-16T16:43:03Z No. of bitstreams: 0 | en |
dc.description.provenance | Made available in DSpace on 2023-08-16T16:43:03Z (GMT). No. of bitstreams: 0 | en |
dc.description.tableofcontents | 致謝 i
摘要 iii Abstract iv Contents v List of Figures viii List of Tables x Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Proposed Techniques 4 1.3 Assumptions 7 1.4 Contributions 9 1.5 Organization 10 Chapter 2 Background 11 2.1 Transition Delay Fault Testing 11 2.2 Delay Fault Diagnosis 13 2.2.1 Improve Diagnosis Resolution by Additional Test 13 2.2.2 Improve Diagnosis Resolution by Other Sources 15 2.3 Volume Diagnosis 16 Chapter 3 Observation 18 3.1 Delay Failure Subset Characteristics 18 3.2 Reasons for Subset Relationships 19 3.2.1 Different Delay Sizes 19 3.2.2 Manufacturing Variations 20 Chapter 4 Proposed Techniques 22 4.1 Build TF Subset Graph 24 4.1.1 Build Subset Table & Similarity Table 25 4.1.2 Transform to Directed Graph 25 4.1.3 Merge Strongly Connected Components (SCCs) 26 4.1.4 Remove Transitive Edges 27 4.2 Identify Systematic Subset Group 29 4.3 Select Representative Test Failures 31 4.4 Analyze & Evaluate Common Suspects 33 4.4.1 Analyze Common Suspects 34 4.4.2 Evaluate Common Suspects 34 Chapter 5 Experimental Results 36 5.1 Experimental Setup 36 5.2 Effectiveness of Identifying Systematic Delay Failures 38 5.3 Diagnosis Resolution Improvement of Delay Faults 42 5.4 Evaluation of Final Suspects 45 Chapter 6 Discussion 47 6.1 Diagnosis with Different Mode 47 6.2 Threshold Settings of Our Proposed Technique 48 6.3 Handling Exception in Subset Relationship Analysis 50 Chapter 7 Conclusion 53 References 55 | - |
dc.language.iso | en | - |
dc.title | 利用子集關係進行系統性延遲錯誤診斷 | zh_TW |
dc.title | Diagnosis of Systematic Delay Failures through Subset Relationship Analysis | en |
dc.type | Thesis | - |
dc.date.schoolyear | 111-2 | - |
dc.description.degree | 碩士 | - |
dc.contributor.oralexamcommittee | 黃俊郎;呂學坤 | zh_TW |
dc.contributor.oralexamcommittee | Jiun-Lang Huang;Shyue-Kung Lu | en |
dc.subject.keyword | 系統性缺陷,診斷與偵錯,延遲錯誤, | zh_TW |
dc.subject.keyword | systematic defect,diagnosis and debug,transition delay fault, | en |
dc.relation.page | 58 | - |
dc.identifier.doi | 10.6342/NTU202302389 | - |
dc.rights.note | 同意授權(限校園內公開) | - |
dc.date.accepted | 2023-08-09 | - |
dc.contributor.author-college | 電機資訊學院 | - |
dc.contributor.author-dept | 電子工程學研究所 | - |
顯示於系所單位: | 電子工程學研究所 |
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