一個具有時間數位轉換器和數位延遲轉換器線性化技術應用於頻率鍵移調變之小數型全數位鎖相迴路

Abstract

本論文實現一個基於小數型全數位鎖相迴路兩點調製架構，在所提出的兩點調製器中，利用前饋消除技術消除兩信號注入點間的路徑延遲擴展。此架構採用計數器為基礎的數位鎖相迴路以達到極短的鎖定時間，時間數位轉換器運用亞時間數位轉換器對應環形振盪器多相位輸出降低單位數位轉換器所需偵測範圍，時間數位轉換器採用雙內插法克服時間數位轉換器因跳頻造成的增益誤差，並仍保有良好的線性度。以數位時間轉換器在回授路徑添加額外的噪聲抖動，隨機化時間數位轉化器的輸入信號，以降低鎖相迴路輸出之小數突波。 此鎖相迴路系統操作於1.2V，共花費6.71 mA電流，輸入參考時脈信號頻率為40 MHz，可輸出信號頻率為23.5至24.5 GHz，採用TSMC 90奈米製程設計，在2.4000390625 GHz下，所量測到的小數突波為-39 dBc。在2.4 GHz下，所量測的相位雜訊於1 MHz頻率偏移下為-99 dBc/Hz，由1 kHz積分到100 MHz的均方根抖動為2.24 ps，FoMJitter為-223dB。

The thesis implement a Two-Point Modulation (TPM) architecture based on a fractional-N all digital phase-locked loop. In the proposed two-point modulator, the feedforward cancellation technique is used to eliminate the path delay spread between two signal injection points. This architecture uses a counter-based digital phase-locked loop to achieve extremely short lock times. The Time-to-Digital Converter (TDC) utilizes a set of sub-TDCs that correspond to the multi-phase output of the ring oscillator. This approach helps in reducing the detection range required for each individual sub-TDC. The converter adopts double interpolation method to overcome the TDC conversion gain error caused by frequency hopping, and still maintains good linearity. Noise dithering at the feedback path by a Digital-to-Time Converter (DTC) randomizes the TDC input signal pattern so that the fractional spur of the PLL output is reduced. The TPM architecture is implemented in the design a 2.35-2.45 GHz ADPLL. Fabricated in the TSMC 90-nm CMOS technology, the whole system dissipates 6.71 mA from a 1.2 V supply and the active area is 0.108 mm2. At 2.4000390625 GHz, the fractional spur is -39 dBc. At 2.4 GHz, the phase noise measured at 1 MHz offset is -99 dBc/Hz. RMS jitter integrated from 1 kHz to 100 MHz is 2.24 ps and figure-of-merit (FOM) is -223 dB.