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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 胡振國 | zh_TW |
dc.contributor.advisor | Jenn-Gwo Hwu | en |
dc.contributor.author | 沈祐德 | zh_TW |
dc.contributor.author | Yu-Te Shen | en |
dc.date.accessioned | 2023-08-08T16:43:42Z | - |
dc.date.available | 2023-11-09 | - |
dc.date.copyright | 2023-08-08 | - |
dc.date.issued | 2023 | - |
dc.date.submitted | 2023-06-16 | - |
dc.identifier.citation | [1] A. S. Sedra et al., Microelectronic Circuits, 8th ed., Oxford University, 2020.
[2] Y. K. Lin and J. G. Hwu, “Photo-Sensing by Edge Schottky Barrier Height Modulation Induced by Lateral Diffusion Current in MOS(p) Photodiode,” IEEE Transactions on Electron Devices, vol. 61, no. 9, pp. 3217-3222, Sep. 2014. [3] C. Y. Yang and J. G. Hwu, “Photo-Sensitivity Enhancement of HfO2-based MOS Photodiode with Specific Perimeter Dependency due to Edge Fringing Field Effect,” IEEE Sensors Journal, vol. 12, no. 6, pp. 2313-2319, Jun. 2012. [4] D. Beckmeiera and H. Baumgärtner, “Metal-Oxide-Semiconductor Diodes Containing C60 Fullerenes for Non-Volatile Memory Applications,” J. Appl. Phys., vol. 113, no. 4, pp. 044520, Jan. 2013. [5] R. Padmanabhan et al., “Dynamical Properties of Optically Sensitive Metal-Insulator-Semiconductor Nonvolatile Memories Based on Pt Nanoparticles,” IEEE Transactions on Nanotechnology, vol. 15, no. 3, pp. 492-498, May 2016. [6] C.-C. Wang et al., “Memory Characteristics of Au Nanocrystals Embedded in Metal-Oxide-Semiconductor Structure by Using Atomic-Layer-Deposited Al2O3 as Control Oxide,” J. Phys. D: Appl. Phys., vol. 40, no. 4, 2007. [7] C. S. Liao and J. G. Hwu, “Subthreshold Swing Reduction by Double Exponential Control Mechanism in an MOS gated-MIS Tunnel Transistor,” IEEE Transactions on Electron Devices, vol. 62, no. 6, pp. 2061-2065, Jun. 2015. [8] C. F. Yang, P. J. Chen, W. C. Chen, K. W. Lin, and J. G. Hwu, “Gate Oxide Local Thinning Mechanism Induced Sub-60 mV/Decade Subthreshold Swing on Charge-Coupled MIS(p) Tunnel Transistor,” IEEE Transactions on Electron Devices, vol.61, no. 1, pp. 279-285, Jan. 2019. [9] W. Chen, C. Yang, and J. Hwu, “Enhanced Two States Current in Mos-Gated MIS Separate Write/Read Storage Device by Oxide Soft Breakdown in Remote Gate,” IEEE Transactions on Nanotechnology, vol. 18, pp. 62-67, 2019. [10] K. Tseng, C. Liao, and J. Hwu, “Enhancement of Transient Two-States Characteristics in Metal-Insulator-Semiconductor Structure by Thinning Metal Thickness,” IEEE Transactions on Nanotechnology, vol. 16, no. 6, pp. 1011-1015, 2017. [11] A. Gehring and S. Selberherr, “Modeling of Tunneling Current and Gate Dielectric Reliability for Nonvolatile Memory Devices,” IEEE Transactions on Device and Materials Reliability, vol. 4, pp. 306-319, 2004. [12] C. W. Liu, W. T. Liu, M. H. Lee, W. S. Kuo, and B. C. Hsu, “A Novel Photodetector Using MOS Tunneling Structures,” IEEE Electron Device Letters, vol. 21, no. 6, pp. 307-309, 2000. [13] Yen-Hao Shih and Jenn-Gwo Hwu, “An On-Chip Temperature Sensor by Utilizing a MOS Tunneling Diode,” IEEE Electron Device Letters, vol. 22, no. 6, pp. 299-301, 2001. [14] C. C. Lin, P. L. Hsu, L. Lin and J. G. Hwu, “Investigation on Edge Fringing Effect and Oxide Thickness Dependence of Inversion Current in MOS Tunneling Diodes with Comb-Shaped Electrodes,” Journal of Applied Physics, vol. 115, no. 12, pp. 124109-1~124109-6, Mar. 2014. [15] T. M. Wang, C. H. Chang, and J. G. Hwu, “Enhancement of Temperature Sensitivity of Metal-Oxide-Semiconductor (MOS) Tunneling Temperature Sensors by Utilizing Hafnium Oxide (HfO2) Film Added on Silicon Dioxide (SiO2),” IEEE Sensors Journal, vol. 6, no. 6, pp. 1468-1472, Dec. 2006. [16] S. -W. Huang and J. -G. Hwu, “Transient Current Enhancement in MIS Tunnel Diodes with Lateral Electric Field Induced by Designed High-Low Oxide Layers,” IEEE Transactions on Electron Devices, vol. 68, no. 12, pp. 6580-6585, Dec. 2021. [17] A. Shaker, M. El Sabbagh, M. El-Banna, “Impact of Nonuniform Gate Oxide Shape on TFET Performance: A Reliability Issue” Physica E: Low-dimensional Systems and Nanostructures, vol. 106, pp. 346-351, 2019. [18] N.N. Reddy, D.K. Panda, “Performance Analysis of Z-Shaped Gate Dielectric Modulated (DM) Tunnel Field-Effect Transistor-(TFET) Based Biosensor with Extended Horizontal N+ Pocket.” Int. J. Numer. Model Electron. Netw. Devices Fields, vol. 34, 2021. [19] Q. Z. Zhang, M. N. Kozicki and D. K. Schroder, “The Effects of Nonuniform Oxide Thickness on MOSFET Performance,” IEEE Transactions on Electron Devices, vol. 35, no. 8, pp. 1395-1397, Aug. 1988. [20] J. H. Chen, K. C. Chen and J. G. Hwu, “Energy-Saving Logic Gates Utilizing Coupling Phenomenon Between MIS(p) Tunneling Diodes,” IEEE Transactions on Electron Devices, vol. 68, no. 12, pp. 6558-6562, Dec. 2021. [21] T. Hsu and J. Hwu, “Prolonged Transient Behavior of Ultrathin Oxide MIS-Tunneling Diode Induced by Deep Depletion of Surrounded Coupling Electrode,” IEEE Transactions on Electron Devices, vol. 67, no. 8, pp. 3411-3416, Aug. 2020. [22] S. K. Ghandhi, VLSI Fabrication Principles: Silicon and Gallium Arsenide, 2nd ed., Wiley-Interscience, 1994. [23] P. F. Schmidt, and W. Michael, “Anodic Formation of Oxide Films on Silicon,” J. Electrochem. Soc., vol. 104, no. 4, pp. 230-236, Apr. 1957. [24] ”Atlas User’s Manual”, 2016. Accessed on: June 9, 2021. [Online]. Available: https://silvaco.com. [25] T.-H. Chiang and J.-G. Hwu, “Ultra-Low Subthreshold Swing in Gated MIS(p) Tunnel Diodes with Engineered Oxide Local Thinning Layers,” IEEE Transactions on Electron Devices, vol. 67, no. 4, pp. 1887-1893, 2020. [26] K.-W. Lin and J.-G. Hwu, “Improved Low-Voltage Sensing Performance in MIS(p) Tunnel Diodes by Oxide Thickening at the Gate Fringe,” IEEE Transactions on Electron Devices, vol. 67, no. 4, pp. 1845-1851, 2020. [27] A. P. G. C. Jain and B. C. Chakravarty, “On the Mechanism of the Anodic Oxidation of Si at Constant Voltage,” J. Electrochem. Soc., vol. 126, no. 1, pp. 89-92, 1979. [28] Y.-C. Yang, K.-W. Lin, and J.-G. Hwu, “Transient Two-State Characteristics in MIS(p) Tunnel Diode with Edge-Thickened Oxide (ETO) Structure,” ECS Journal of Solid State Science and Technology, vol. 9, p. 103006, 2020. [29] Y.-K. Lin, L. Lin, and J.-G. Hwu, “Minority Carriers induced Schottky Barrier Height Modulation in Current Behavior of Metal-Oxide-Semiconductor Tunneling Diode,” ECS J. Solid State Sci. Technol., vol. 3, no. 6, pp. Q132-Q135, 2014. [30] J.-Y. Cheng and J.-G. Hwu, “Characterization of Edge Fringing Effect on the C-V Responses from Depletion to Deep Depletion of MOS(p) Capacitors with Ultrathin Oxide and High-κ Dielectric,” IEEE Transactions on Electron Devices, vol. 59, no. 3, pp. 565-572, 2012. [31] N. W. Ashcroft and N. D. Mermin, Solid State Physics, Saunders College Publishing, 1976. [32] C.-S. Liao and J.-G. Hwu, “Current Coupling Effect in MIS Tunnel Diode with Coupled Open-Gated MIS Structure,” ECS Trans., vol. 75, no. 5, pp.77-86, Oct. 2016. | - |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/88195 | - |
dc.description.abstract | 本論文探討了金屬-絕緣層-半導體穿隧二極體元件內部與外部的耦合效應。在第二章中,我們設計出一個側向氧化層厚度不均勻的金屬-氧化層-半導體穿隧二極體元件。我們發現當元件從順偏壓切換到接地時,短路電流並非隨著時間單調遞減,而是會在一段時間後出現一個極大值。透過反覆的實驗與SILVACO TCAD 軟體的模擬,我們提出了一種由氧化層不均勻的結構所導致的載子傳輸與複合機制。由於這種機制發生在元件內部,因此我們將其命名為內部耦合效應。在第三章中,我們改良了前人所研究過的鄰近同心金屬-絕緣層-半導體穿隧二極體。透過實驗數據,我們證明了改良後的邏輯元件,不僅面積縮減了99%以上,更具備承載更多輸入端且低功耗的特性。由於這是由多個電極組合所產生的效應,因此我們將其命名為外部耦合效應。最後,我們針對內部耦合效應提出了可能的記憶體應用,也針對如何進一步改良元件設計使得外部耦合效應更理想給出了具體的建議。 | zh_TW |
dc.description.abstract | In this dissertation, the inner and outer charge coupling phenomena in metalinsulation-semiconductor (MIS) tunneling diodes (TDs) are investigated. In Chapter 2, we design a metal-oxide-semiconductor tunneling diode with a non-uniform oxide thickness in the lateral direction. We found that the short-circuit current does not decrease monotonically with time when the device is switched from forward-bias to ground. Instead, a peak occurs after a period of time. Through experimental results and simulations with SILVACO TCAD, we propose a carrier transport and recombination relaxation mechanism caused by the lateral non-uniform structure of the oxide layer. Since this mechanism occurs inside the device, we named it as inner coupling phenomenon. In Chapter 3, we modify the previously studied adjacent concentric metalinsulator-semiconductor tunneling diodes. By the experimental results, we demonstrate that the modified logic device not only has a reduced area of more than 99%, but also is capable of carrying more inputs while maintains low power consumption. Since this is an effect results from the combination of multiple electrodes, we named it as outer coupling phenomenon. Finally, we propose a possible memory application utilizing the inner coupling effect, and give specific suggestions on how to design the device structure to make outer coupling effect even more preferable. | en |
dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2023-08-08T16:43:42Z No. of bitstreams: 0 | en |
dc.description.provenance | Made available in DSpace on 2023-08-08T16:43:42Z (GMT). No. of bitstreams: 0 | en |
dc.description.tableofcontents | 誌謝 I
摘要 II Abstract III Contents V Figure Captions VII Chapter 1:Introduction 1 1-1 Motivation and Thesis Organization 2 1-2 Lateral Nonuniformity:High-low Oxide Structure 3 1-3 Coupled MIS Tunneling Diode 4 1-4 Oxide Growth Mechanism:Anodic Oxidation 4 1-5 TCAD Simulation 5 1-6 Summary 7 Chapter 2:Inner Coupling:Carrier Transport Mechanism of Injection-then-Ground Operated MIS Tunneling Diode with High-low Oxide Structure 9 2-1 Introduction 10 2-2 Experimental and TCAD Simulation 11 2-3 Result and Discussion 12 2-3-1 Transient Peak Current 12 2-3-2 Carrier Transport Mechanism 13 2-3-3 Bias Voltage Effect and the Role of NCR 16 2-3-4 High-Low Oxide Ratio Effect 16 2-3-5 Endurance and Power Consumption 17 2-4 Summary 18 Chapter 3:Outer Coupling:Multi-Level Characteristics of Scaled Ultrathin Oxide MIS(p) Tunneling Diode by Utilizing Charge Coupling Mechanism with Open Voltage Sensing 30 3-1 Introduction 31 3-2 Experimental 32 3-3 Results and Discussion 33 3-3-1 Current- and Capacitance-Voltage Characteristics 33 3-3-2 Multi-level Characteristics 34 3-3-3 Endurance and Performance 35 3-4 Summary 36 Chapter 4:Conclusion and Future Work 40 4-1 Conclusion 41 4-2 Future Work 41 4-2-1 Control of the Inner Coupling:Oxide Thickness and Device Size 41 4-2-2 Possible Application of Inner Coupling:A Novel Memory Device 42 4-2-3 Design Strategy of Outer Coupling:Multi-level Characteristics 43 Reference 44 | - |
dc.language.iso | zh_TW | - |
dc.title | 金屬-絕緣層-半導體穿隧二極體內部與外部耦合效應之研究 | zh_TW |
dc.title | Investigation on Inner and Outer Charge Coupling Phenomena in Metal-Insulator-Semiconductor Tunneling Diodes | en |
dc.type | Thesis | - |
dc.date.schoolyear | 111-2 | - |
dc.description.degree | 碩士 | - |
dc.contributor.oralexamcommittee | 吳幼麟;胡璧合 | zh_TW |
dc.contributor.oralexamcommittee | You-Lin Wu;Pi-Ho Hu | en |
dc.subject.keyword | 金氧半穿隧二極體,邏輯元件,記憶體,側向不均勻性,耦合效應, | zh_TW |
dc.subject.keyword | MIS TDs,coupling phenomenon,lateral non-uniformity,memory,logic device, | en |
dc.relation.page | 48 | - |
dc.identifier.doi | 10.6342/NTU202301035 | - |
dc.rights.note | 同意授權(限校園內公開) | - |
dc.date.accepted | 2023-06-16 | - |
dc.contributor.author-college | 電機資訊學院 | - |
dc.contributor.author-dept | 電子工程學研究所 | - |
顯示於系所單位: | 電子工程學研究所 |
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