以低溫多晶矽薄膜電晶體製程設計之開迴路壓控振盪器類比數位訊號轉換器

Abstract

本論文利用低溫多晶矽薄膜半導體製程於塑膠材質之基板上實作了一開迴路壓控振盪器為主之類比數位轉換器晶片，由於低溫多晶矽薄膜半導體製程具有相當大程度的製程變異及較低的能源使用效率，本電路具備之高度數位化的特性使其較能夠克服在製作中會遇到的製程與環境變異帶來之影響，主體壓控振盪器亦是由單顆振盪器取代傳統製程中常用的差動結構，避免再在此製程中產生更多不匹配，同時採用了基於反向器所設計之轉導器做為振盪器前端以增加功耗使用效率，並導入系統層級斬波器的結構去消除整體系統的輸入偏移電壓及閃爍雜訊。本晶片之量測設定於輸入範圍為1.5 VDC，電壓源5 V，此晶片核心面積為4.76平方毫米，操作於5伏電壓源下僅需0.381 毫瓦功耗。有效位元數經過量測在頻寬為9.76 Hz下達到8.6有效位元數，在品質因素方面達到FoMs = 97.74 dB及FoMw = 47.19 nJ/conv。

This work presents a Voltage-Controlled Oscillator (VCO)-based Analog-to-Digital Converter implemented on the LTPS-TFT process. This work is designed for DC sensing applications. It is fabricated using the LTPS-TFT 3μm process. Despite TFT's characteristics, such as large process variation and poor power efficiency, its ability to be manufactured on flexible substrates can create plenty of new applications. This work features a highly digital topology and a system-level chopping technique. It also employs a robust ring oscillator due to its digital-friendly structure. The self-biased inverter-based OTA is used not only improving power efficiency but also constructing robust inner negative feedback. Making the system has better robustness under LTPS-TFT’s large mismatch. To further enhance the ADC performance, a system-level chopper is used to reduce the impact of flicker noise and offset voltage induced by TFT. The measurement was conducted with 1.5 V DC input. The total power consumption in this work is 0.381 mW under a 5 V supply voltage. The core area is 4.76 mm2. The measured ENOB achieves 8.6 within a 9.76 Hz bandwidth. It results in the corresponding FoM of 97.74 dB and FoMw of 47.19 nJ/conv.