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  1. NTU Theses and Dissertations Repository
  2. 電機資訊學院
  3. 電子工程學研究所
請用此 Handle URI 來引用此文件: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/87720
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dc.contributor.advisor李峻霣zh_TW
dc.contributor.advisorJiun-Yun Lien
dc.contributor.author何志力zh_TW
dc.contributor.authorChih-Li Heen
dc.date.accessioned2023-07-19T16:06:12Z-
dc.date.available2023-11-09-
dc.date.copyright2023-07-19-
dc.date.issued2023-
dc.date.submitted2023-05-10-
dc.identifier.citationM. Bohr and K. Mistry, "Intel’s Revolutionary 22 nm Transistor Technology," [Online]. Available: https://download.intel.com/newsroom/kits/22nm/pdfs/22nm-Details_Presentation.pdf.
K. Rim, S. Koester, M. Hargrove, J. Chu, P. M. Mooney, J. Ott, T. Kanarsky, P. Ronsheim, M. Ieong, A. Grill and H.-S. P. Wong, "Strained Si NMOSFETs for High Performance CMOS Technology," Symposium on VLSI Technology, pp. 59- 60, 6 2001.
K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Brazier, M. Buehler, A. Cappellani, R. Chau, C.-H. Choi, G. Ding, K. Fischer, T. Ghani, R. Grover, W. Han, D. Hanken, M. Hattendorf, J. He, J. Hicks , R. Huessner, D. Ingerly, P. Jain, R., "A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging," IEEE International Electron Devices Meeting (IEDM), pp. 247-250, 12 2007.
Jeff Desjardins, "Visualizing Moore’s Law in Action (1971-2019)," 9 12 2019. [Online]. Available: www.visualcapitalist.com/visualizing-moores-law-in-action-1971-2019/.
"International Roadmap for Devices and Systems 2022 Edition: More Moore," 2022. [Online].
C.W. Liu , M. Östling , and J.B. Hannon , Guest Editors, "New materials for post-Si computing," Materials Research Society, vol. 39, pp. 658-662, 2014.
Pere Miró, Martha Audiffred and Thomas Heine, "An atlas of two-dimensional materials," Chem. Soc. Rev. 43, Vols. 6537-6554, 2014.
S. Gupta, B. Magyari-Köpe, Y. Nishi, and K. C. Saraswat, "Achieving direct band gap in germanium through integration of Sn alloying and external strain," Journal of Applied Physics, vol. 7, no. 113, p. 073707, 2013.
L. Liu, R. Liang, J. Wang, and J. Xu, "Enhanced Carrier Mobility and Direct Tunneling Probability of Biaxially Strained Ge1-xSnx Alloys for Field-Effect Transistors Applications," Journal of Applied Physics, vol. 18, no. 117, p. 184501, 2015.
K. L. Low, Y. Yang, G. Han, W. Fan, and Y.-C. Yeo, "Electronic band structure and effective mass parameters of Ge1-xSnx alloys," Journal of Applied Physics, vol. 10, no. 112, p. 103715, 2012.
Kai-Ying Tien, “Electron Transport and Simulation of Band Structures of GeSn Alloys,” Master thesis, National Taiwan University."
Yen Chuang, “High Electron Mobility in Strained GeSn n-MOSFETs by Chemical Vapor Deposition,” Doctoral Dissertation, National Taiwan University.
C. Yadav, “Compact modeling of capacitance and current in silicon and III – V transistors,” Ph.D. dissertation, Indian Institute of Technology Kanpur, India, 2016.
Chia-You Liu, “Optical, Tunneling, and Carrier Transport Properties in GeSn Epitaxial Films,” Doctoral Dissertation, National Taiwan University.
C. Schulte-Braucks et al., "Process modules for GeSn nanoelectronics with high Sn-contents," Solid-State Electronics, no. 128, p. 54, 2017.
M. Liu, G. Han, Y. Liu, C. Zhang, H. Wang, X. Li, J. Zhang, B. Cheng, and Y. Hao, "Undoped Ge0.92Sn0.08 Quantum Well PMOSFETs on (001), (011) and (111) Substrates with in Situ Si2H6 Passivation: High Hole Mobility and Dependence of Performance on Orientation," 2014 Symposium on VLSI Technology, pp. 1-2, 2014.
Genquan Han, Shaojian Su, Chunlei Zhan, Qian Zhou, Yue Yang, Lanxiang Wang, Pengfei Guo, Wang Wei, Choun Pei Wong, Ze Xiang Shen, Buwen Cheng and Yee-Chia Yeo, "High-mobility germanium-tin (GeSn) P-channel MOSFETs featuring metallic source/drain and sub-370 °C process modules," IEEE International Electron Devices Meeting (IEDM), pp. 402-404, 12 2011.
Yuye Kang, Kaizhen Han, Eugene Y.-J. Kong, Dian Lei, Shengqiang Xu, Ying Wu, Yi-Chiau Huang and Xiao Gong, "The First GeSn Gate-All-Around Nanowire P- FET on the GeSnOI Substrate with Channel Length of 20 nm and Subthreshold Swing of 74 mV/decade," International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), pp. 112-112, 4 2019.
Dian Lei, Kwang Hong Lee, Shuyu Bao, Wei Wang, Saeid Masudy-Panah, Sachin Yadav, Annie Kumar, Yuan Dong, Yuye Kang, Shengqiang Xu, Ying Wu, Yi-Chiau Huang, Hua Chung, Schubert S. Chu, Satheesh Kuppurao, Chuan Seng Tan, Xiao Gong and Yee-Chia Yeo, "The First GeSn FinFET on a Novel GeSnOI Substrate Achieving Lowest S of 79 mV/decade and Record High Gm,int of 807 μS/μm for GeSn P-FETs," Symposium on VLSI Technology, pp. 198-199, 6 2017.
Y.-S. Huang, F.-L. Lu, Y.-J. Tsou, C.-E. Tsai, C.-Y. Lin, C.-H. Huang, and C. W. Liu,, "First Vertically Stacked GeSn Nanowire pGAAFETs with Ion= 1850 μA/μm (Vov = Vds = -1V) on Si by GeSn/Ge CVD Epitaxial Growth and Optimum Selective Etching," 2017 IEEE International Electron Devices Meeting, p. 37, 2017.
S. Gupta, B. Vincent, D. H. C. Lin, M. Gunji, A. Firrincieli, F. Gencarelli, B. Magyari-Köpe, B.Yang, B. Douhard, J. Delmotte, A. Franquet, M. Caymax, J. Dekoster, Y. Nishi and K.C. Saraswat, "GeSn Channel nMOSFETs: Material Potential and Technological Outlook," ,” Symposium on VLSI Technology, pp. 95-96, 6 2012.
S. Gupta, B. Vincent, B. Yang, D. Lin, F. Gencarelli, J.-Y. J. Lin, R. Chen, O. Richard, H. Bender, B. Magyari-Köpe, M. Caymax, J. Dekoster, Y. Nishi and K. C. Saraswat, "Towards high mobility GeSn channel nMOSFETs: Improved surface passivation using novel ozone oxidation method," IEEE International Electron Devices Meeting (IEDM), pp. 375-378, 12 2012.
Genquan Han, Shaojian Su, Lanxiang Wang, Wei Wang, Xiao Gong, Yue Yang, Ivana, Pengfei Guo, Cheng Guo, Guangze Zhang, Jisheng Pan, Zheng Zhang, Chunlai Xue, Buwen Cheng and Yee-Chia Yeo, "Strained germanium-tin (GeSn) N-channel MOSFETs featuring low temperature N+/P junction formation and GeSnO2 interfacial layer," Symposium on VLSI Technology, pp. 97-98, 6 2012.
Pengfei Guo, Chunlei Zhan, Yue Yang, Xiao Gong, Bin Liu, Ran Cheng, Wei Wang, Jisheng Pan, Zheng Zhang, Eng Soon Tok, Genquan Han and Yee-Chia Yeo, "Germanium-Tin (GeSn) N-channel MOSFETs with low temperature silicon surface passivation Publisher: IEEE," International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), pp. 82-83, 4 2013.
Yung-Chin Fang, Kuen-Yi Chen, Ching-Heng Hsieh, Chang-Chia Su and Yung- Hsien Wu, "N-MOSFETs Formed on Solid Phase Epitaxially Grown GeSn Film with Passivation by Oxygen Plasma Featuring High Mobility," ACS Applied Materials and Interfaces, , pp. 26374-26380, 11 2015.
Tzu-Hung Liu, Po-Yuan Chiu, Yen Chuang, Chia-You Liu, Chang-Hong Shen, Guang-Li Luo and Jiun-Yun Li, "High-Mobility GeSn n-Channel MOSFETs by Low-Temperature Chemical Vapor Deposition and Microwave Annealing," IEEE Electron Device Letters, vol. 39, no. 4, pp. 468-471, 2018.
Y. Chuang, C.-Y. Liu, G.-L. Luo, and J.-Y. Li, "Electron Mobility Enhancement in GeSn n-Channel MOSFETs by Tensile Strain," IEEE Electron Device Letters, vol. 42, no. 1, pp. 10-13, 2021.
H. Li, Y. X. Cui, K. Y. Wu, W. K. Tseng, H. H. Cheng, and H. Chen, "Strain relaxation and Sn segregation in GeSn epilayers under thermal treatment," Applied Physics Letters, vol. 102, no. 251907, p. 1, 2013.
Y.-S. Huang, F.-L. Lu, Y.-J. Tsou, H.-Y. Ye, S.-Y. Lin, W.-H. Huan, and C.-W. Liu, "Vertically Stacked Strained 3-GeSn-Nanosheet pGAAFETs on Si Using GeSn/Ge CVD Epitaxial Growth and the Optimum Selective Channel Release Process," IEEE Electron Device Letters, vol. 9, no. 39, pp. 1274-1277, 2018.
Ravi Pillarisetty, "Academic and industry research progress in germanium nanodevices," Nature, no. 479, pp. 324-328, 2011.
Jay Deep Sau and Marvin L. Cohen, "Possibility of increased mobility in Ge-Sn alloy system," PHYSICAL REVIEW B, vol. 045208, no. 75, pp. 1-7, 2007.
J. Mitard, L. Witters, Y. Sasaki, H. Arimura, A. Schulze, R. Loo, L.-Å. Ragnarsson, A. Hikavyy, D. Cott, T. Chiarella, S. Kubicek, H. Mertens, R. Ritzenthaler, C. Vrancken, P. Favia, H. Bender, N. Horiguchi, K. Barla, D. Mocuta, A. Mocuta, N. Collaert and, "A 2nd Generation of 14/16nm-node compatible strained-Ge pFINFET with improved performance with respect to advanced Si- channel FinFETs," Symposium on VLSI Technology, pp. 27-28, 6 2016.
J. D. Gallagher, C. L. Senaratne, P. Sims, T. Aoki, J. Menéndez, and J. Kouvetakis, "Electroluminescence from GeSnheterostructure pin Diodes at the Indirect Todirect Transition," Applied Physics Letters, vol. 9, no. 106, p. 091103, 2015.
R. W. Olesinski and G. J. Abbaschian, "The Ge−Sn (Germanium−Tin) System," Bulletin of Alloy Phase Diagrams, vol. 3, no. 5, pp. 265-271, 1984.
Chi-Woo Lee, Aryan Afzalian, Nima Dehdashti Akhavan, Ran Yan, Isabelle Ferain and Jean-Pierre Colinge, "Junctionless multigate field-effect transistor," Applied Physics Letters, vol. 053511, no. 94, pp. 1-2, 2009.
O. Kononchuk and B. Y. Nguyen, "Silicon-On-Insulator (SOI) Technology: Manufacture and Applications," WOODHEAD PUBLISHING, 2014.
J.P. Colinge, A. Kranti, R. Yan, C.W. Lee, I. Ferain, R. Yu, N. Dehdashti Akhavan and P. Razavi, "Junctionless nanowire transistor (JNT): Properties and design guidelines," Solid-State Electronics, no. 65-66, pp. 33-37, 2011.
H.-S. Lan, and C. W. Liu, "Band Alignments at Strained Ge1-xSnx/Relaxed Ge1- ySny Heterointerfaces," Journal of Physics D: Applied Physics, vol. 13, no. 50, p. 13, 2017.
Kuo-Hsing Kao, Anne S. Verhulst, Maarten Van de Put, William G. Vandenberghe, Bart Soree, Wim Magnus, and Kristin De Meyer, "Tensile strained Ge tunnel field-effect transistors: k · p material modeling and numerical device simulation," Journal of Applied Physics, vol. 044505, no. 115, pp. 1-8, 2014.
Y.-J. Yang, W. S. Ho, C.-F. Huang, S. T. Chang, and C. W. Liu, "Electron Mobility Enhancement in Strained-Germanium n-Channel Metal-Oxide- Semiconductor Field-Effect Transistors," Applied Physics Letters, vol. 10, no. 91, 2007.
Wei Wang, Dian Lei, Yuan Dong, Xiao Gong, Eng Soon Tok and Yee-Chia Yeo, "Digital Etch Technique for Forming Ultra-Scaled Germanium-Tin (Ge1−xSnx) Fin Structure," Scientific Reports, vol. 1835, pp. 1-9, 2017.
Shinji Migita, Yukinori Morita, Meishoku Masahara and Hiroyuki Ota, "Electrical performances of junctionless-FETs at the scaling limit (LCH= 3 nm)," IEEE International Electron Devices Meeting (IEDM), pp. 191-194, 12 2012.
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dc.identifier.urihttp://tdr.lib.ntu.edu.tw/jspui/handle/123456789/87720-
dc.description.abstract鍺(錫)材料具有高遷移率的特性,非常有潛力成為下一代電晶體(MOSFETs)的通道材料。鍺錫的電洞遷移率能透過施加壓縮應力提升;另一方面,當錫比例高達8-11%或施加拉伸應歷時,鍺錫材料則會轉變為直接能隙,這種能隙轉變能增加聚集在Γ能帶的電子數量,減少等效電子質量,進而提高電子遷移率。雖然p-型鍺錫電晶體已經有相當成熟的研究,n-型鍺錫電晶體的研究相對較少。
本論文探討了鍺錫材料的電晶體製作及特性。鍺錫材料的能隙較小,導致使用該材料製作電晶體時容易產生漏電流,而採用檯面結構來控制源/汲極與基板的PN接面,與傳統平面電晶體相比,能有效地減少漏電流。接著製作無接面鍺錫多閘極電晶體,減少摻雜擴散或退火等熱製程步驟,可提高鍺錫的熱穩定性。最後製作拉伸應變鍺錫檯面結構電晶體,並與鬆弛和壓縮應變的元件進行比較,觀察不同應變對於材料中電子遷移率的影響。
zh_TW
dc.description.abstractGeSn is a promising channel material for next-generation transistors due to its high carrier mobility. Compressive stresses can increase the hole mobility of GeSn, while the electron mobility can be boosted by transforming GeSn into a direct-bandgap material. As the Sn composition is as high as 8 - 11% or subjected to tensile stresses, GeSn becomes a direct bandgap material, which increases the number of electrons accumulated in the Γ-valley. Thus, the electron effective mass is reduced, leading to a higher electron mobility. Although great progress has been made for p-type GeSn transistors, research on n-type GeSn transistors is relatively scarce.
This thesis investigates the fabrication and characteristics of n-type GeSn transistors. The small bandgap of GeSn leads to large leakage current in transistors. Using a mesa structure to control the PN junctions between the source/drain and the substrate, the leakage current is effectively reduced compared to conventional planar transistors. Then junctionless GeSn transistors are demonstrated to improve the thermal budget of GeSn by reducing the steps of thermal processes such as dopant diffusion or annealing. Tensile strained GeSn mesa transistors are characterized and compared to relaxed and compressive-strained devices.
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dc.description.provenanceSubmitted by admin ntu (admin@lib.ntu.edu.tw) on 2023-07-19T16:06:12Z
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dc.description.provenanceMade available in DSpace on 2023-07-19T16:06:12Z (GMT). No. of bitstreams: 0en
dc.description.tableofcontents誌謝 i
摘要 ii
Abstract iii
目錄 iv
圖目錄 vi
第 1 章 引言 1
1.1 簡介 1
1.2 鍺錫金氧半場效電晶體 3
1.3 論文架構 4
第 2 章 n型鍺錫電晶體製作與特性分析 6
2.1 簡介 6
2.2 鍺錫薄膜磊晶與材料分析 8
2.3 鍺錫電晶體製作與電性分析 10
2.3.1 n型鍺錫檯面結構電晶體 10
2.3.2 無接面電晶體簡介 15
2.3.3 鍺錫無接面多閘極電晶體製作與分析 17
2.4 小結 23
第 3 章 n型拉伸應變鍺(錫)電晶體製作與分析 24
3.1 簡介 24
3.2 拉伸應變鍺錫薄膜磊晶與分析 28
3.3 n型拉伸應變鍺錫電晶體製作與分析 30
3.4 小結 35
第 4 章 結論與未來工作 36
4.1 結論 36
4.2 未來工作 36
參考文獻 38
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dc.language.isozh_TW-
dc.subject鍺錫合金zh_TW
dc.subject鰭式電晶體zh_TW
dc.subject檯面結構電晶體zh_TW
dc.subject無接面zh_TW
dc.subject拉伸應變zh_TW
dc.subjectFET with mesa structureen
dc.subjectFinFETsen
dc.subjectjunctionless(JL)en
dc.subjectgermanium-tin (GeSn)en
dc.subjecttensile-straineden
dc.titlen-型鍺錫電晶體製作與分析zh_TW
dc.titleFabrication and characterization of n-type GeSn FETsen
dc.typeThesis-
dc.date.schoolyear111-2-
dc.description.degree碩士-
dc.contributor.oralexamcommittee李敏鴻;廖洺漢zh_TW
dc.contributor.oralexamcommitteeMin-Hung Lee;Ming-Han Liaoen
dc.subject.keyword鍺錫合金,檯面結構電晶體,鰭式電晶體,無接面,拉伸應變,zh_TW
dc.subject.keywordgermanium-tin (GeSn),FET with mesa structure,FinFETs,junctionless(JL),tensile-strained,en
dc.relation.page43-
dc.identifier.doi10.6342/NTU202300782-
dc.rights.note同意授權(限校園內公開)-
dc.date.accepted2023-05-10-
dc.contributor.author-college電機資訊學院-
dc.contributor.author-dept電子工程學研究所-
dc.date.embargo-lift2028-05-09-
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