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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳信樹 | zh_TW |
| dc.contributor.advisor | Hsin-Shu Chen | en |
| dc.contributor.author | 張諺哲 | zh_TW |
| dc.contributor.author | Yen-Che Chang | en |
| dc.date.accessioned | 2023-07-19T16:04:40Z | - |
| dc.date.available | 2023-11-10 | - |
| dc.date.copyright | 2023-07-19 | - |
| dc.date.issued | 2023 | - |
| dc.date.submitted | 2023-05-18 | - |
| dc.identifier.citation | [ 1 ]Y,-S,Hu,et al.,"A 510nW 12-bit 200kS/s SAR-assisted SAR ADC using a re-switching technique", Proc. VLSI Symp., pp. C238-C239, 2017.
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Papers, pp. 458-459, Feb. 2015. [ 8 ] Y.-S. Hu, K.-Y. Lin, and H.-S. Chen, “A 12-bit 200kS/s subranging SAR ADC with an energy-curve reshape technique,” IEEE A-SSCC Dig. Tech. Papers, pp. 149-152, Nov. 2016. [ 9 ] V. Hariprasath,et al. , “Merged capacitor switching based SAR ADC with highest switching energy-efficiency,” IEEE Electronics Letters, vol. 46, no. 9, pp. 620-621, Apr. 2010. [ 10 ]Y. Lim and M. P. Flynn, “A 1mW 71.5dB SNDR 50MS/S 13b fully differential ring-amplifier-based SAR-assisted pipeline ADC,” IEEE ISSCC Dig. Tech. Papers, pp. 458-459, Feb. 2015. [ 11 ]S. Hsieh, et al., "A 0.44fJ/conversion-step 11b 600KS/s SAR ADC with semi-resting DAC," 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), Honolulu, HI, 2016, pp. 1-2. [ 12 ]M. Liu, et al., "A 7.1-fJ/Conversion-Step 88-dB SFDR SAR ADC With Energy-Free “Swap To Reset”," in IEEE Journal of Solid-State Circuits, vol. 52, no. 11, pp. 2979-2990, Nov. 2017. [ 13 ]Y. Chung, et al., "A 12-bit 8.47-fJ/Conversion-Step Capacitor-Swapping SAR ADC in 110-nm CMOS," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, no. 1, pp. 10-18, Jan. 2015. [ 14 ]F. Kuttner, "A 1.2V 10b 20MSample/s non-binary successive approximation ADC in 0.13/spl mu/m CMOS," 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315), San Francisco, CA, USA, 2002, pp. 176-177 vol.1. [15]C. Liu, et al., "A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation," 2010 IEEE International Solid-State Circuits Conference - (ISSCC), San Francisco, CA, 2010, pp. 386-387. [ 16 ]S. Babayan-Mashhadi, et al., "Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 2, pp. 343-352, Feb. 2014. [ 17 ]D. Johns and K. Martin, Analog Integrated Circuit Design, New York, USA: Wiley, 1997. [ 18 ]T. Sepke, P. Holloway, C. G. Sodini, and H. S. Lee, “Noise analysis for comparator-based circuits,” IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 56, no. 3, pp. 541–553, Mar. 2 [ 19 ]Van der goes, F., et al., “A 1.5mW 68dB SNDR 80MS/s 2× Interleaved SAR-Assisted Pipelined ADC in 28nm CMOS,” IEEE ISSCC Dig. Tech. Papers, pp. 200-201, Feb. 2014. [ 20 ]Michael Choi and Asad A. Abidi, “A 6-b 1.3Gsample/s A/D Converter in 0.35-um CMOS,” IEEE JOURNAL OF SOLID-STATE CIRCUIT,VOL36,NO. 12, DECEMBER 2001 [ 21 ]B. Razavi, "The design of a comparator [the analog mind]", IEEE Solid-State Circuits Mag., vol. 12, no. 4, pp. 8-14, Nov. 2020. [ 22 ]B. Razavi, "The StrongARM latch [A Circuit for All Seasons]", IEEE Solid-State Circuits Magazine, vol. 7, no. 2, pp. 12-17, Jun. 2015. [ 23 ]P. M. Figueiredo and J. C. Vital, "Kickback noise reduction techniques for CMOS latched comparators", IEEE Trans. Circuits Syst. II Exp. Briefs, vol. 53, no. 7, pp. 541-545, Jul. 2006. [24]J. Doernberg, H.-S. Lee and D.A. Hodges, "Full-Speed Testing of A/D Converters", IEEE J. Solid-State Circuits, vol. SC-19, pp. 820-827, 1984. [ 25 ]E. A. Vittoz, "Future of analog in the VLSI environment", Proc. IEEE Int. Symp. Circuits Syst., vol. 2, pp. 1372-1375, May 1990. [ 26 ] Calibre xRC User’s Manual [ 27 ] B. P. Ginsburg and A. P. Chandrakasan, "500-MS/s 5-bit ADC in 65-nm CMOS with split capacitor array DAC", IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 739-747, Apr. 2007. [ 28 ]A. Nikoozadeh and B. Murmann, "An analysis of latch comparator offset due to load capacitor mismatch", IEEE Trans. Circuits Syst. II Exp. Briefs, vol. 53, no. 12, pp. 1398-1402, Dec. 2006. [ 29 ] P. Nuzzo, F. De Bernardinis, P. Terreni and G. Van der Plas, "Noise analysis of regenerative comparators for reconfigurable ADC architectures", IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 55, no. 6, pp. 1441-1454, 2008 [ 30 ]W. Yu, S. Sen and B. H. Leung, "Distortion analysis of MOS track-and-hold sampling mixers using time-varying Volterra series", IEEE Trans. Circuits Syst. II Analog Digit. Signal Process., vol. 46, no. 2, pp. 101-113, Feb. 1999. [ 31 ]B. Razavi, "The bootstrapped switch [a circuit for all seasons]", IEEE Solid State Circuits Mag., vol. 7, no. 3, pp. 12-15, Summer 2015. [ 32 ] Hooman Farkhani, “ Fundamentals of Data Converters”, Lecture Slides of Islamic Azad University of Najafabad, Lecture. 3, Feb. 2016 [33]H.-Y.Tai,”Energy Efficient Successive-Approximation Analog-to-Digital Converter”, National Taiwan University Doctoral Dissertation, July,2014 [ 34 ] Y.-S. Liao, “All Digital Calibration for High-Resolution Successive-Approximation Register Analog-to-Digital Converter”, National Taiwan University Master’s Thesis, Oct, 2022 [ 35 ] B. Song, et. al., ”A 10-b 15-MHz CMOS recycling two-step A/D converter,” JSSC1990/12, pp. 1328–1338. [ 36 ] Y.-S.Hu,” Application of the Skipping Switching Algorithm in the Subranging ADC”, National Taiwan University Doctoral Dissertation, Augest,2019 [ 37 ] K.-Y. Lin, “Power-Efficient Successive-Approximation Register Analog-to-Digital Converter”, National Taiwan University Master’s Thesis, July, 2016 [ 38 ] J.-T. Wu, “ Data Conversion Integrated Circuits”, Lecture Slides of National Chiao Tung University, April. 2017 | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/87716 | - |
| dc.description.abstract | 類比數位轉換器可以被廣泛的應用在音頻訊號中。本論文提出一個每秒三百五十萬次的十二位元連續漸進式類比數位轉換器，並實現在0.13微米的製程。此連續漸進式類比數位轉換器是應用在一個喇叭系統的架構中。
此設計為次區間類比數位轉換器。我們使用了偵測與迴避演算法以及重新切換技巧來改善線性度。更甚者，我們有發現裸晶上的內部變異對線性度的影響。取樣電路部分，我們採用底板取樣來避免增益布匹配以及訊號相關的電荷注入。取樣不匹配也有在此論文中被討論。我們使用疊接的動態兩級比較器來節省功耗以及達到十二位元的噪聲規格。比較器的再生輸出錯誤有在此論文中被討論並避免其發生。 在音頻輸入範圍，此次區間連續漸進式類比數位轉換器可以達到十點六一的有效位元、七十三點五四分貝的無雜散訊號動態範圍、以及六十七點零一的信噪比。此作品在四百萬取樣頻率之奈奎斯特輸入時可以達到十點三九的有效位元、七十二點一六分貝的無雜散訊號動態範圍、以及六十五點六四的信噪比。在一點五伏特的供電電壓以及一點二伏特的參考電壓下，此作品的功耗為三百一十五點六微瓦。 | zh_TW |
| dc.description.abstract | An analog-to-digital converter (ADC) can be widely used in audio applications. This thesis presents a 3.5MS/s 12-bit ADC in TSMC 0.13um process. The SAR prototype is for a specially designed speaker system.
This design is a Sub-Ranging successive-approximation register (SAR) ADC. The Detect-and-Skip algorithm and Re-Switching technique are used to improve linearity. Moreover, I noticed how the in-die variation effect affects the linearity. In sampling circuits, I applied bottom-plate sampling to avoid gain mismatch and signal-dependent charge injection. The sampling mismatch is also discussed in this work. I apply the cascoded dynamic two-stage comparator to save power and achieve the 12-bit noise. The regeneration error is also presented. In the audio band, this Sub-Ranging SAR ADC achieves an ENOB of 10.61, an SFDR of 73.54dB, and an SNR of 67.01dB at 1MS/s. Moreover, it achieves an ENOB of 10.39, an SFDR of 72.16dB, and an SNR of 65.64dB at 4MS/s with Nyquist rate input. It consumes 315.6uW with a 1.5V supply and a 1.2V reference voltage. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2023-07-19T16:04:40Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2023-07-19T16:04:40Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 論文口試委員審定書 ii
致謝 iii 摘要 v ABSTRACT vii CONTENTS viii LIST OF FIGURES xii LIST OF TABLES xvi Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 2 Chapter 2 Fundamentals of Analog-to-Digital Converters 3 2.1 Introduction 3 2.2 Static Performance 3 2.2.1 Offset Error 3 2.2.2 Gain Error 4 2.2.3 Differential and Integral Nonlinearity 5 2.3 Spectral Performance 7 2.3.1 Signal-to-Noise Ratio (SNR) 7 2.3.2 Total Harmonic Distortion (THD) 8 2.3.3 Spurious-Free Dynamic Range (SFDR) 9 2.3.4 Signal-to-Noise and Distortion Ratio (SNDR) 9 2.3.5 Effective Number of Bits (ENOB) 10 2.3.6 Figure of Merit (FoM) 10 2.4 ADC Architectures 12 2.4.1 Flash Architecture 12 2.4.2 Pipeline Architecture 13 2.4.3 Two-Step and Sub-Ranging Architecture 14 2.4.4 Successive-Approximation-Register (SAR) Architecture 15 Chapter 3 High-Resolution and Low-Power SAR ADC 17 3.1 Introduction 17 3.1.1 Conventional Asynchronous SAR ADC Design 17 3.1.2 Bottleneck of High-Resolution SAR ADC 21 3.2 High-Resolution DAC Design 21 3.2.1 Settling Time 22 3.2.2 Sampling Noise 24 3.2.3 Capacitor Mismatch 25 3.2.4 Switching Methods with Average Switching Energy 28 3.3 Comparator 34 3.3.1 Offset Voltage 38 3.3.2 Input-Referred Noise 39 3.3.3 Kickback Noise 41 3.4 Summary 43 Chapter 4 A 3.5 MS/s 12-Bit Sub-Ranging SAR ADC Using a Re-Switching Technique with Offset Calibration 45 4.1 Introduction 45 4.2 Proposed Architecture 47 4.3 Cap Array Switching and its Design Consideration 50 4.3.1 Detect-and-Skip (DAS) Algorithm 50 4.3.2 DAC Re-Switching Technique 54 4.3.3 Aligned Switching Technique 58 4.3.4 DAC Switching Methods 60 4.3.5 Linearity Analysis and the In-Die Variation Effect 61 4.4 Sampling 66 4.4.1 Sampling Mismatch 67 4.5 Comparator Design 69 4.5.1 Noise 70 4.5.2 Offset 72 4.5.3 Threshold Voltage Relationship 73 4.6 Offset Cancellation Combined with Digital Error Correction Circuits 75 4.6.1 Offset Detection and Adjustment 76 Chapter 5 Experiment Results 78 5.1 Measurement Environment 78 5.2 Measurement Results 79 Chapter 6 Conclusions and future work 89 6.1 Conclusion 89 6.2 Future Work 89 Chapter 7 Bibliography 90 | - |
| dc.language.iso | en | - |
| dc.subject | 連續漸進式類比數位轉換器 | zh_TW |
| dc.subject | SAR ADC | en |
| dc.title | 一個使用重新切換技巧並搭配輸入位移電壓校正的三百五十萬取樣速率的十二位元次區間連續漸進式類比數位轉換器 | zh_TW |
| dc.title | A 3.5 MS/s 12-Bit Sub-Ranging SAR ADC Using a Re-Switching Technique with Offset Calibration | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 111-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 戴宏彥;胡耀升 | zh_TW |
| dc.contributor.oralexamcommittee | Hung-Yen Tai;Yao-Sheng Hu | en |
| dc.subject.keyword | 連續漸進式類比數位轉換器, | zh_TW |
| dc.subject.keyword | SAR ADC, | en |
| dc.relation.page | 93 | - |
| dc.identifier.doi | 10.6342/NTU202300823 | - |
| dc.rights.note | 同意授權(限校園內公開) | - |
| dc.date.accepted | 2023-05-18 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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