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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳信樹 | zh_TW |
| dc.contributor.advisor | Hsin-Shu Chen | en |
| dc.contributor.author | 王奕倫 | zh_TW |
| dc.contributor.author | Yi-Lun Wang | en |
| dc.date.accessioned | 2023-07-19T16:04:15Z | - |
| dc.date.available | 2023-11-09 | - |
| dc.date.copyright | 2023-07-19 | - |
| dc.date.issued | 2023 | - |
| dc.date.submitted | 2023-05-15 | - |
| dc.identifier.citation | [1] “TPM 1.2 Main Specification.” Trusted Computing Group. (2019, September 6). Retrieved April 1, 2023, from https://trustedcomputinggroup.org/resource/tpm-main-specification/
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Schmitt-Landsiedel, "Yield and speed optimization of a latch-type voltage sense amplifier," in IEEE Journal of Solid-State Circuits, vol. 39, no. 7, pp. 1148-1158, July 2004, doi: 10.1109/JSSC.2004.829399. [38] Y. He, D. Li, Z. Yu and K. Yang, "ASCH-PUF: A “Zero” Bit Error Rate CMOS Physically Unclonable Function With Dual-Mode Low-Cost Stabilization," in IEEE Journal of Solid-State Circuits, doi: 10.1109/JSSC.2022.3233373. [39] M. J. M. Pelgrom, A. C. J. Duinmaijer and A. P. G. Welbers, "Matching properties of MOS transistors," in IEEE Journal of Solid-State Circuits, vol. 24, no. 5, pp. 1433-1439, Oct. 1989, doi: 10.1109/JSSC.1989.572629. [40] J. Guajardo, S. S. Kumar, G.-J. Schrijen, and P. Tuyls, “FPGA Intrinsic PUFs and Their Use for IP Protection,” Cryptogr. Hardw. Embed. Syst. - CHES 2007, pp.63–80. [41] Y. Su, J. Holleman, and B. Otis, “A1.6pJ/blt 96% stable chip-ID generating circuit using process variations,” in Digest of Technical Papers - IEEE International Solid-State Circuits Conference, 2007. [42] A. Basak, S. Paul, J. Park, J. Park and S. Bhunia, "Reconfigurable ECC for adaptive protection of memory", Proc. IEEE 56th Int. Midwest Symp. Circuits Syst. (MWSCAS), pp. 1085-1088, Aug. 2013. [43] Vincent Leest, Bart Preneel, and Erik Sluis. “Soft Decision Error Correction for Compact Memory-Based PUFs Using a Single Enrollment.” In Emmanuel Prouff and Patrick Schaumont, editors, Cryptographic Hardware and Embedded Systems CHES 2012, volume 7428 of Lecture Notes in Computer Science, pages 268–282. Springer Berlin Heidelberg, 2012. 1.3, 3.7.1, 5, 5.2.3, 6 [44] R. Maes, P. Tuyls and I. Verbauwhede, "A soft decision helper data algorithm for SRAM PUFs," 2009 IEEE International Symposium on Information Theory, Seoul, Korea (South), 2009, pp. 2101-2105, doi: 10.1109/ISIT.2009.5205263. [45] J. Lee, D. Lee, Y. Lee and Y. Lee, "A 445F2 leakage-based physically unclonable Function with Lossless Stabilization Through Remapping for IoT Security," 2018 IEEE International Solid - State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2018, pp. 132-134, doi: 10.1109/ISSCC.2018.8310219. [46] “NIST SP 800-22: Documentation and Software - Random Bit Generation: CSRC.” Computer Security Division, Information Technology Laboratory. Retrieved May 11, 2023, from https:// https://csrc.nist.gov/projects/random-bit-generation/documentation-and-software | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/87715 | - |
| dc.description.abstract | 本論文提出了一個利用可替代配置技術的新架構，來實現一個靜態隨機存取記憶體物理不可仿製功能電路。
為了減輕物理不可仿製功能電路中糾錯碼的使用，必須要降低物理不可仿製功能電路原生數據的位元錯誤率。然而，由於閾值電壓在製程中的不匹配為隨機分布，靜態隨機存取記憶體物理不可功能函數電路存儲單元的穩定性一直以來都不夠理想。在這裡提出的可替代配置架構中，我使用可替代的電晶體作為存儲單元內的第二熵源。新的熵源讓每個存儲單元有了二次生成穩定位元的機會，進而提升物理不可仿製功能電路的穩定性。 為了進一步提高穩定性，我們透過一個斜坡訊號作為電源供應來緩慢啟動存儲單元。在這個作品中也應用了偏置接地電壓的技巧來選擇需要屏蔽的不穩定位元。 本文提出的物理不可仿製功能電路使用180納米CMOS製程實現。在2.2V的供電下，每個位元的功耗為4370fJ。電路在20~70℃的溫度下正常運作，屏蔽暗位元後量測得到1.4*10-4的位元錯誤率。隨機性為53.1%，唯一性為45.6%。 | zh_TW |
| dc.description.abstract | This thesis presents a static random-access memory (SRAM) physical unclonable function (PUF) based on a new alternative configuration architecture.
To lighten the use of error-correcting code (ECC) in PUF, the bit error rate (BER) of raw data from PUF must be as low as possible. SRAM PUF bit cell has an unfavorable native-BER due to the random distribution of threshold voltage mismatch. The proposed work can increase native stability by using the alternative transistors as the second entropy source in each bit cell. The new configuration brings another chance to produce stable bits. To further increase the stability, the power-up process of the PUF cell is controlled at a slow ramp rate. The VSS-biased preselection is also applied in this work to complete masking for dark bits. The proposed SRAM PUF is fabricated in a 180-nm CMOS process. The PUF core consumes 4370 fJ/bit under a 2.2-V supply. The PUF is measured functional under the temperature of 20~70℃, and the measured native-BER is 1.4 * 10-4 after masking. Randomness is 53.1%, and uniqueness is 45.6%. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2023-07-19T16:04:14Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2023-07-19T16:04:15Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 致謝 I
摘要 II Abstract III Contents IV List of Figures VI List of Tables IX Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 4 Chapter 2 Fundamentals of Physical Unclonable Function 5 2.1 Introduction 5 2.2 PUF Concept 6 2.2.1 Challenge-Response Pair 6 2.2.2 PUF Key Generation Flow 7 2.2.3 PUF Applications 8 2.3 Performances 9 2.3.1 Randomness – Hamming Weight 9 2.3.2 Uniqueness – Inter-Hamming Distance 10 2.3.3 Stability – Bit Error Rate 10 2.4 Types of PUF 11 2.4.1 Weak PUF 11 2.4.2 Strong PUF 12 2.5 PUF Architectures 12 2.5.1 Arbiter PUF 12 2.5.2 Ring-oscillator PUF 13 2.5.3 SRAM PUF 14 Chapter 3 PUF Error Reduction and Correction for High Stability 20 3.1 Introduction 20 3.2 PUF Stabilization Technique 20 3.2.1 Temporal Majority Voting 21 3.2.2 Dark Bit Masking 22 3.2.3 Indirect Preselection 23 3.2.4 Hardening 24 3.2.5 Remapping 26 3.2.6 Reconfiguring 27 3.3 Error-correcting Code 29 3.4 Summary 30 Chapter 4 An SRAM PUF with High Native-stability Using Alternative Configuration Technique 31 4.1 Introduction 31 4.2 Proposed Architecture 33 4.3 Alternative Configuration Technique 36 4.3.1 Enhancement-enhancement SRAM (EE SRAM) 36 4.3.2 Alternative Configuration Implementation 38 4.4 Power-up Ramp Rate Control 41 4.5 VSS Bias for Indirect Preselection 48 4.6 PUF Control Logic and Peripheral Circuit 50 4.6.1 Main Control Block 50 4.6.2 BL Track 52 4.6.3 WL Decoder and Ramp-up Signal Generator 53 4.6.4 Read Circuit 53 4.7 Simulation Results 54 Chapter 5 Experiment Results 58 5.1 Environment Setup and Initial Measurement 58 5.2 Measurement Discussion 60 5.2.1 WL Signal Wiring Error 61 5.2.2 Control Signal Glitch and Power Supply Voltage Drop 63 5.3 Measurement Results 65 Chapter 6 Conclusions and Future Works 70 6.1 Conclusions 70 6.2 Future Works 71 6.2.1 Error Corrections 71 6.2.2 Circuit Improvements 71 Bibliography 74 | - |
| dc.language.iso | en | - |
| dc.subject | 暗位元屏蔽 | zh_TW |
| dc.subject | 偏置接地電壓預選 | zh_TW |
| dc.subject | 可替代配置 | zh_TW |
| dc.subject | 靜態隨機存取記憶體 | zh_TW |
| dc.subject | 物理不可仿製功能 | zh_TW |
| dc.subject | 電源啟動速率控制 | zh_TW |
| dc.subject | physical unclonable function (PUF) | en |
| dc.subject | power-up rate control | en |
| dc.subject | VSS-biased preselection | en |
| dc.subject | alternative configuration | en |
| dc.subject | static random-access memory (SRAM) | en |
| dc.subject | dark-bit masking | en |
| dc.title | 一個利用全新可替代配置架構的高原生穩定性靜態隨機存取記憶體物理不可仿製功能電路 | zh_TW |
| dc.title | An SRAM PUF with High Native-Stability Using Alternative Configuration Technique | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 111-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 洪崇智;劉宗德;陳君朋 | zh_TW |
| dc.contributor.oralexamcommittee | Chung-Chih Hung;Tsung-Te Liu;Jiun-Peng Chen | en |
| dc.subject.keyword | 靜態隨機存取記憶體,物理不可仿製功能,可替代配置,電源啟動速率控制,偏置接地電壓預選,暗位元屏蔽, | zh_TW |
| dc.subject.keyword | static random-access memory (SRAM),physical unclonable function (PUF),alternative configuration,power-up rate control,VSS-biased preselection,dark-bit masking, | en |
| dc.relation.page | 82 | - |
| dc.identifier.doi | 10.6342/NTU202300810 | - |
| dc.rights.note | 同意授權(限校園內公開) | - |
| dc.date.accepted | 2023-05-16 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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