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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/87644完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳奕君 | zh_TW |
| dc.contributor.advisor | I-Chun Cheng | en |
| dc.contributor.author | 蔡侑廷 | zh_TW |
| dc.contributor.author | Yu-Ting Tsai | en |
| dc.date.accessioned | 2023-07-11T16:05:07Z | - |
| dc.date.available | 2024-09-25 | - |
| dc.date.copyright | 2023-07-11 | - |
| dc.date.issued | 2022 | - |
| dc.date.submitted | 2002-01-01 | - |
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/87644 | - |
| dc.description.abstract | 本研究使用層離法（exfoliation）來獲取二維過渡金屬硫化物（Transition Metal Dichalcogenides, TMDs/ TMDCs）中的二硫化鎢（tungsten disulfide, WS2）作為電晶體之主動層，並與另一種絕緣二維材料六方晶氮化硼搭配，來探討不同的六方晶氮化硼與二硫化鎢晶體堆疊方式所產生之電性表現差異。與化學氣相沉積等長晶方式相比，透過層離法所獲得之晶體有著較少的缺陷，因而可以更好的研究此種材料本身的物理性質，以及其作為電晶體的電性表現。 本研究首先探討堆疊結構對於電晶體特性的影響，使用單層結構二硫化鎢之二維電晶體的次臨界擺幅為2.71 V/dec，開關電流比為~104，而其場效載子遷移率在常溫下可以達到 85.2 cm2V-1s-1，在5K的低溫之下更高達566.4 cm2V-1s-1，代表其極具潛力，可做為下一世代的半導體材料。引入六方晶氮化硼作為二硫化鎢下方之緩衝層的雙層堆疊結構，次臨界擺幅獲得改善，但場效載子遷移率與開關電流比卻下降，其原因可能是六方晶氮化硼緩衝層過厚，雖能減少介面缺陷，但等效絕緣層厚度也相對增加，導致閘極偏壓對於電晶體的控制力下降。在雙層結構之上，引入六方晶氮化硼作為二硫化鎢上方之封裝層的六方晶氮化硼/二硫化鎢/六方晶氮化硼三明治結構電晶體，則能有效阻絕環境中的水氣及氧氣對元件造成的影響，因此場效載子遷移率、次臨界擺幅與開關電流比均得到改善。接著針對引入六方晶氮化硼之雙層及三明治結構的電晶體進行了變溫分析，但在低溫情況下的電性表現與預期中不一致，包括載子遷移率及開關電流比均不增反減，顯示本研究的電晶體載子傳輸是由變程跳躍機制所主導，代表堆疊晶體製程中還有問題需要被解決，才能使得電晶體之載子傳輸機制變為band-like transport機制。 最後針對不同退火處理條件進行探討，將未經退火處理、氬氣退火處理以及氬氫混氣退火處理後之三明治結構二硫化鎢電晶體進行比較。結果顯示，所有退火處理條件均能改善電晶體之電性表現，但也會造成電晶體之開啟電壓（Von）與臨界電壓（Vth）偏移，這源自於二硫化鎢本身於退火處理後形成的硫空缺以及吸附於元件上之水氣與氧氣的移除，此兩種現象都等效於添加N-型摻雜物至二硫化鎢通道層中。本研究也對二硫化鎢的物理性質進行相關的探討，例如系統中之非線性非交互性傳輸效應（nonreciprocal transport effect, NRTE）。此現象可於非中心對稱系統中，二硫化鎢晶體結構正是屬於此類非中心對稱系統。倘若能加以改善接觸電阻的相關問題，便能將二維電晶體實用化之願景向前推進一步，也能對二維材料本身之諸多物理性質進行更深入的研究及探討。 | zh_TW |
| dc.description.abstract | In this thesis, the exfoliation method was employeed to prepare two-dimensional (2D) tungsten disulfide (WS2), which is one of the 2D transition metal dichalcogenides (TMDs or TMDCs) commonly used as the semiconductor layer for 2D field-effect transistors (FETs). The 2D materials obtained by the scotch tape exfoliation method have lower defect density and better crystal quality than those obtained by epitaxial methods such as the chemical vapor deposition (CVD) and solution fabrication. Thus, it’s easier to investigate the intrinsic properties via these exfoliated 2D materials. First, we invesgtiage the effect of devce structure on the performance of 2D FETs. The 2D WS2 FET with a single-layered structure has a subthreshold swing of 2.71 V/dec, on/off current ratio of ~ 104. Its field-effect mobility reaches 85.2 cm2V-1s-1 at room temperarure and 566.4 cm2V-1s-1 at 5 K, showing a great potential for next-generation semiconductor device applications. The Hexagonal-boron nitride (hBN) layer is then introduced as the buffer and/or encapsulation layer. The 2D WS2 FET with a double-layered strucurture, hBN underneath WS2, exhibits improved subthreshold swing but lower field-effect mobility and on/off current ratio. Although the insersion of hBN buffer layer can reduce the interface defect states between WS2 and SiO2, but the gate modulation becomes weaker since the effective thickness of the gate dielectric increases. Next, an additional hBN layer is introduced on top of the WS2 channel to form a sandwich strucurture to prevent the influence of moisture and oxygen in the atmosphere. The 2D FET with a sandwich structure indeed shows improved electrical performance in terms of the field-effect mobility, subthreshold swing and on/off current ratio. The temperature-dependent electrical characteristics of 2D WS2 FETs with the double-layered and sandwich structures are further investigated. Both the mobility and on/off ratio decrease as the temperature reduces, implying the carrier transport mechanism is dominated by Variable Range Hopping (VRH). To realize band-like transport in the 2D WS2 FETs with double-layered and sandwich structures, the contact resistance and stacking procedure must be optimized. Finally, the effect of thermal annealing is studied. The electrical performance of 2D WS2 FETs with a sandwich structure is improved after thermal annealing in Ar or Ar/H2 environment. Negative shifts of on voltage (Von) amd threshold voltages (Vth) are observed after the thermal annealing because of the formation of sulfur vacancies and removal of adsorbed mosture and oxygen, both acting as donors in WS2 FETs. Nevertheless, the contact resistance of the FET is still high compared with other researches. This issue must be resolved prior to further investigating the intrinsic physical properties of 2D WS2. Such as the non-reciprocal transport effect in the non-centrosymmetric WS2 system discussed in this thesis. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2023-07-11T16:05:07Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2023-07-11T16:05:07Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 目錄 誌謝 I 中文摘要 II Abstract IV 目錄 VI 圖目錄 X 表目錄 XVIII 第一章 緒論 1 1.1 研究背景 1 1.2 研究動機與目的 3 1.3 論文架構 4 第二章 理論基礎與文獻回顧 6 2.1 電晶體簡介 6 2.1.1 二維電晶體之結構 6 2.1.2 二維電晶體之工作原理 8 2.1.3 二維電晶體之特徵參數 9 2.2 二維材料簡介 14 2.2.1 二硫化鎢簡介 14 2.2.2 氮化硼簡介 17 2.3 二維電晶體之文獻回顧 19 2.3.1 二維電晶體之結構變化 24 2.3.2 金屬電極的材料選擇、能帶彎曲與接觸電阻 28 2.3.3 金屬電極接觸方式 36 2.3.4 退火處理 42 2.3.5 穿隧式金屬/絕緣層/半導體結構電晶體 53 第三章 實驗方法與步驟 58 3.1 二維晶體製程 58 3.1.1 膠帶層離法 58 3.1.2 乾式轉移技術 60 3.2 薄膜沉積製程 64 3.2.1 射頻磁控濺鍍 64 3.2.2 電子束蒸鍍 67 3.3 微影製程 68 3.3.1 光學微影製程 68 3.3.2 電子束微影製程 71 3.4 打線接合 73 3.4.1 打線接合機 73 3.4.2 銀膠金線手動接合 75 3.5 二維二硫化鎢電晶體製備流程 76 3.5.1 二硫化鎢單層結構電晶體 77 3.5.2 二硫化鎢/六方晶氮化硼雙層結構電晶體 78 3.5.3 氮化硼/二硫化鎢/氮化硼三明治結構電晶體 79 3.6 量測分析方法 82 3.6.1 電晶體電流-電壓量測方法 82 3.6.2 電晶體電流-電壓變溫量測方法 83 3.6.3 電晶體第二諧波量測方法 84 3.6.4 原子力顯微鏡 85 3.6.5 微拉曼光譜儀 87 3.6.6 快速光學對比度厚度檢定法 88 第四章 結果與討論 90 4.1 二硫化鎢之材料特性 90 4.1.1 原子力顯微鏡 90 4.1.2 微拉曼光譜儀 92 4.1.3 快速光學對比度厚度檢定法 93 4.2 氮化硼之材料特性 94 4.2.1 原子力顯微鏡 94 4.2.2 微拉曼光譜儀 96 4.2.3 快速光學對比度厚度檢定法 97 4.3 二維二硫化鎢電晶體之基本電特性分析 99 4.4 二維二硫化鎢電晶體結構變化之電特性分析 101 4.5 二維二硫化鎢電晶體之變溫電特性分析 105 4.6 二維二硫化鎢電晶體之不同條件退火處理電特性分析 109 4.6.1 退火對於雙層結構電晶體電性表現之影響 109 4.6.2 不同退火條件下的三層結構電晶體之基本電特性分析 111 4.6.3 不同退火條件下的三層結構電晶體之變溫電特性分析 114 4.6.4 三層結構電晶體之四點量測接觸電阻分析 120 4.7 三層結構電晶體之第二諧波電阻分析 123 第五章 結論與未來展望 128 5.1 結論 128 5.2 未來展望 129 A. 附錄 130 A.1 各元件之退火條件與晶體厚度表 130 A.2 元件 #1 之二維晶體堆疊圖 131 A.3 元件 #2 之二維晶體堆疊圖 132 A.4 元件 #3 之二維晶體堆疊前/後圖 133 A.5 元件 #4 之二維晶體堆疊前/後圖 135 A.6 元件 #5 之二維晶體堆疊前/後圖 137 A.7 不同結構下的二硫化鎢電晶體之變溫轉換特性曲線 139 A.8 一維金屬線接觸之二硫化鎢電晶體 140 參考文獻 147 圖目錄 圖 2.1 典型的下閘極二維電晶體結構示意圖，使用高摻雜濃度之矽基板作為下閘極電極[25] 7 圖 2.2 典型的n型電晶體之（a）轉換特性曲線（b）輸出特性曲線[26] 9 圖 2.3 過渡金屬硫化物之（a）單層結構側視圖（僅以一組分子示意）（b）單層結構俯視圖（c）層狀結構 示意圖[27] 14 圖 2.4 使用密度泛函理論計算出的二硫化鎢能帶結構圖[28] 15 圖 2.5（a）二硫化鉬的拉曼振動模式（b）二硫化鉬的拉曼光譜，黑線為波峰的位置，紅線為兩種振動模式峰值的差異[27] 16 圖 2.6 （a）不同層數二硫化鎢之拉曼光譜（b）不同層數下之波峰差值與強度比值[32] 16 圖 2.7（a）六方晶氮化硼於高解像能電子顯微鏡下的成像（b）結構示意圖[33] 17 圖 2.8（a）氮化硼的拉曼光譜（b）拉曼位移的峰值[49] 18 圖 2.9 B. Radisavljevic et al.製作之具有二氧化鉿介電層的二硫化鉬場效電晶體（a）電晶體結構圖（b）轉換特性曲線[18] 20 圖 2.10 Hwang et al.所製作的二硫化鎢電晶體之（a）轉換特性曲線（b）輸出特性曲線[55] 20 圖 2.11 不同結構的二硫化鎢電晶體之轉換特性曲線，黑線為對數尺度，藍線違憲性尺度（a）單層二硫化鎢結構（b）雙層二硫化鎢/六方晶氮化硼結構（c-d）三明治結構[60] 26 圖 2.12 不同結構的二硫化鎢電晶體之輸出特性曲線（a）單層結構（b）三明治結構，表示此元件的電極是屬於歐姆接觸[60] 26 圖 2.13 隨著溫度變化的（a）三層結構之線性坐標軸轉換特性曲線（b）三明治結構之最大開狀態汲極電流（c）不同結構下之載子遷移率[60] 27 圖 2.14 金屬的功函數與TMDs的電子親和力，圖右側為插入緩衝層後之金屬功函數的計算結果[91] 30 圖 2.15 二硫化鎢電晶體的TEM成像[89]（a）整體元件成像（b）通道層成像（c-d）鈀與鈦電極下，變形之二硫化鉬通道層 31 圖 2.16 使用金覆蓋層之銦電極二硫化鉬電晶體（a）電晶體結構示意圖（b）掃描穿透式電子顯微鏡（STEM）之介面成像圖（c）TLM分析之接觸電阻（d-e）與其它種接觸電阻改善方法之比較圖（f）電晶體之轉換特性曲線（g）電晶體之輸出特性曲線[70] 32 圖 2.17 使用鈀覆蓋層之銦電極二硒化鎢電晶體（a）金屬/半導體介面處之STEM成像，其介面處與二硫化鉬電晶體一樣，有著清晰的凡得瓦結構接觸（b-c）與金覆蓋層之銦電極二硒化鎢電晶體相比之轉換特性曲線與輸出特性曲線，整體金屬電極之功函數確實有提高，提高P型載子之傳輸表現（d-e）與其它研究之接觸電阻與載子濃度比較圖[70] 33 圖 2.18 一維線接觸金屬電極之製作方法示意圖[94]（A）石墨烯與定義完成之光阻（B）電漿處理（C）電漿處理完成之後，會直接沉積金屬（D）使用TLM（Transfer Length Method）結構的石墨烯一維線接觸元件示意圖，右上角為側視圖 36 圖 2.19 線接觸與面接觸之（a）示意圖（b）比較表[94] 37 圖 2.20 不同電漿處理時間下，一維金屬電極線接觸之（A）總電阻對不同通道長度（B）TLM分析得出之接觸電阻對電漿處理時間（C~F）不同電漿處理時間之石墨烯蝕刻示意圖[94] 38 圖 2.21 金屬電極轉移法（TVC）與傳統電極接觸差異示意圖[107] 39 圖 2.22 轉移法與沉積法對於二維材料的（a-b）影響示意圖和（c-d）穿透式電子顯微鏡下的結構與損傷[105] 40 圖 2.23 雙層二硒化鎢電晶體[107]（a）不同製程之轉換特性曲線，可以看出大氣環境對元件的影響，以及TVC能使金屬電極的接觸變好（b）該元件的穩定性測試，可以看出元件幾乎沒有劣化。 41 圖 2.24 在HPA處理前後的二硫化鉬電晶體之（a）轉換特性曲線，元件的S.S.從1.6降低至1.1 V/dec（b）亞能帶DOS與能量作圖[111] 43 圖 2.25 二硫化鉬電晶體於HPA處理過程中的（a）示意圖與（b）沿著電晶體垂直方向的能帶圖（c）可以看到原本在二維材料中的原子逸散到外界所形成的硫空缺使得費米能階往導帶靠近（d）亞能帶能態密度g（E）減少之示意圖[111] 44 圖 2.26 不同元件於製作完成後，保存於真空中三個月/隨後暴露於大氣之中一天/再次進行後退火處理之輸出特性曲線[110] 46 圖 2.27 在HPHA處理前/後的元件表現之（a）轉換特性曲線（b）飽和汲極電流（c）接觸電阻（d）蕭特基能障[112] 46 圖 2.28 二硫化鎢電晶體經歷不同退火處理時長之（a）對數尺度轉換特性曲線（b）薄膜電導率對閘極電壓圖（c）元件電阻對退火時間圖（d）場效載子遷移率對退火時間圖（c-d）之中，黑色資料點代表著兩點量測之結果，紅色資料點代表四點量測之結果[59] 48 圖 2.29 不同退火溫度對於二硫化鉬電晶體之（a）轉換特性曲線（b）場效載子遷移率[109] 49 圖 2.30 二硫化鉬電晶體之TOF-SIMS分析（a）退火處理前（b）400 ℃退火處理後[109] 49 圖 2.31 邊緣接觸元件於不同退火處理條件下的（a-c）轉換特性曲線（d）接觸電阻（e）載子遷移率[102] 50 圖 2.32 MS與MIS結構電晶體之輸出特性曲線（a-b）鉻電極（c-d）銦電極[136] 54 圖 2.33 穿隧式MIS結構電晶體的原理示意圖（a）無六方晶氮化硼作為穿隧層時的能帶結構（b）六方晶氮化硼能阻隔較深能帶中的缺陷，使蕭特基能障降低（c）此種結構產生之偶極子也能降低蕭特基能障[138] 54 圖 2.34 穿隧式金屬/絕緣層/半導體結構電晶體之（a）載子遷移率（b）接觸電阻 隨著溫度變化作圖[136] 55 圖 2.35 銦作為電極時，有無穿隧層造成的能帶差異示意圖[136] 56 圖 2.36 不同金屬電極引入穿隧層後的（a）蕭特基能障與（b）接觸電阻 隨著金屬功函數作圖[136] 57 圖 3.1（左）膠帶層離法示意圖與（右）膠帶層離法撕貼次數與晶體層數和面積的簡單模型[157] 59 圖 3.2 單層石墨烯（SLG）的乾式轉移過程示意圖及說明[170] 62 圖 3.3（a）透過雷射進行局部加溫的SMP 轉移技術（b）可以結合步進馬達來達成自動轉印技術[169] 63 圖 3.4 射頻磁控濺鍍系統示意圖[171] 66 圖 3.5 電子束蒸鍍系統示意圖[172] 67 圖 3.6於基板上塗佈之雙層光阻凹割結構 69 圖 3.7 本研究中使用之光罩圖形，有16個可供量測之電極，右側插圖則為中間部分之圖形，進行電子束微影時會透過使用四個十字對齊標誌，每個十字的長寬均為10 μm 70 圖 3.8 TPT HB-10 Wire Bonder[177] 74 圖 3.9 不同結構之二硫化鎢電晶體示意圖（a）單層結構二硫化鎢電晶體（b）雙層結構二硫化鎢電晶體（c）單次乾式轉移三明治結構之二硫化鎢電晶體（d）分次乾式轉移三明治結構之二硫化鎢電晶體 81 圖 3.10 原子力顯微鏡示意圖[178] 86 圖 3.11（A）在顯微鏡體下的晶體照片（B）原子力顯微鏡對該晶體的成像，圖片頂部提供了圖片底部虛線路徑的高度資訊（C）將圖片進行處理後所得到的對比度資訊，可以看到不同的層數有著不同的光學對比度[193] 89 圖 4.1 不同層數之二硫化鎢於（a）光學顯微鏡（OM）下之圖像（b）原子力顯微鏡（AFM）之成像，圖中之紅線與綠線分別對應了該處的AFM成像高度圖，圖中紅線之不同晶體區域厚度。 91 圖 4.2（a）不同層數的二硫化鎢晶體之微拉曼光譜（b）不同層數之二硫化鎢晶體兩種主要振動模式：面內振動模式E2g與面外振動模式A1g之特徵峰差值（紅線）與峰值強度比例（藍線） 92 圖 4.3 使用層離法獲取之不同層數二硫化鎢的厚度與光學對比度作圖。橫軸是於光學顯微鏡下之晶體與基板的對比度，縱軸則是原子力顯微鏡所獲得之晶體厚度。 93 圖 4.4 較少層數之六方晶氮化硼於（a）光學顯微鏡（OM）下之圖像（b）原子力顯微鏡（AFM）之成像，圖中之紅線與綠線分別對應了該處的AFM成像高度圖。 94 圖 4.5 較多層數之六方晶氮化硼於（a）光學顯微鏡（OM）下之圖像（b）原子力顯微鏡（AFM）之成像，圖中之紅線對應了該處的AFM成像高度圖。 95 圖 4.6 六方晶氮化硼之拉曼光譜 96 圖 4.7 層離法獲取之不同層數六方晶氮化硼的厚度與光學對比度作圖，橫軸是於光學顯微鏡下之晶體與基板的（a）灰階影像（b）綠色通道（c）紅色通道之光學對比度，縱軸則是使用原子力顯微鏡獲得之晶體厚度。 98 圖 4.8 不同厚度之六方晶氮化硼晶體於（a）光學顯微鏡（OM）下之影像（b）綠色通道之影像（c）藍色通道之影像（d）紅色通道之影像 98 圖 4.9 二硫化鎢/二氧化矽單層結構電晶體於常溫下之（a）轉換特性曲線（b）輸出特性曲線 100 圖 4.10 二維二硫化鎢電晶體之轉換特性曲線與輸出特性曲線（a）（b）單層結構 （c）（d）雙層結構（e）（f）三明治結構 103 圖 4.11 不同結構下的二硫化鎢電晶體之變溫轉換特性曲線，左圖之縱軸為對數尺度，右圖之縱軸為線性尺度，分別為（a）二硫化鎢單層結構（b）二硫化鎢/六方晶氮化硼雙層結構（c）六方晶氮化硼/二硫化鎢/六方晶氮化硼三明治結構。 107 圖 4.12 不同結構二硫化鎢電晶體之載子遷移率對溫度作圖 108 圖 4.13 雙層結構二硫化鎢電晶體之退火前後的轉換特性曲線 109 圖 4.14 雙層結構二硫化鎢電晶體之輸出特性曲線於（a）退火處理前（b）退火處理後 110 圖 4.15 於常溫下的三層結構二硫化鎢電晶體之（a）與（b）分別為尚未經過退火處理之轉換特性曲線與輸出特性曲線。（c）與（d）則為經過氬氣退火處理之轉換特性曲線與輸出特性曲線。（e）與（f）則為經過氬氫混合氣體退火處理之轉換特性曲線與輸出特性曲線 112 圖 4.16 變溫過程中的三層結構二硫化鎢電晶體之（a）與（b）分別為尚未經過退火處理之對數座標軸轉換特性曲線與線性座標軸轉換特性曲線。（c）與（d）則為經過氬氣退火處理之對數轉換特性曲線與線性轉換特性曲線。（e）與（f）則為經過氬氫混合氣體退火處理之對數轉換特性曲線與線性轉換特性曲線 116 圖 4.17 三明治結構於不同退火處理條件之（a）場效載子遷移率對溫度圖（b）開啟電流對溫度圖 117 圖 4.18 未經退火處理之三明治結構電晶體於（a）溫度5 K與（b）溫度300 K下之轉換特性曲線（黑線）與閘極漏電流（藍線） 117 圖 4.19 不同元件之電阻與溫度關係圖（對數尺度）（a）元件#1單層結構電晶體，右上插圖為電阻R與溫度T之關係圖（b）元件#2雙層結構電晶體（c）元件#5三明治結構無退火處理電晶體（d）元件#3三明治結構氬氣退火處理之電晶體 118 圖 4.20 四點量測方法之電晶體結構示意圖（a）俯視圖（b）側視圖 121 圖 4.21 三明治結構二硫化鎢電晶體之（a）轉換特性曲線。實心資料點為四點量測，不同顏色之資料線代表四點量測之兩側量測電極（V+與V-）電壓差；空心資料點則為兩點量測，不同顏色之資料線代表兩點量測之汲極源極電壓差。（b）接觸電阻與閘極偏壓圖 122 圖 4.22 不同退火條件三明治結構二硫化鎢電晶體於低溫下之–元件#4之氬氫混氣退火處理（a）第一諧波電阻（b）第二諧波電阻（c）對應之轉換特性曲線，圖中的黑色虛線為電晶體開關狀態切換處，該處之閘極偏壓為7 V；元件#3之氬氣退火處理（d）第一諧波電阻（e）第二諧波電阻（f）對應之轉換特性曲線，圖中的黑色虛線為電晶體開關狀態切換處，該處之閘極偏壓為10 V 125 圖 4.23 不同退火條件三明治結構二硫化鎢電晶體於5 K下之輸出特性曲線（a）元件#4之氬氫退火處理（b）元件#3之氬氣退火處理 127 圖 A.1 單層結構二硫化鎢電晶體，圖中四個角落之十字長寬均為10 μm。 131 圖 A.2 雙層結構二硫化鎢電晶體，電極接觸於二硫化鎢晶體之兩端。圖中四個角落之十字長寬均為10 μm。 132 圖 A.3 三明治結構二硫化鎢電晶體之堆疊過程，其中圖片左下角之十字對齊標誌長寬均為10 μm。（a）二硫化鎢堆疊於六方晶氮化硼緩衝層時，其中較小之晶體為二硫化鎢（b）沉積完金屬電極後（c）用以作為封裝層之六方晶氮化硼（d）完成堆疊之三明治結構二硫化鎢電晶體 133 圖 A.4 三明治結構二硫化鎢電晶體於未堆疊完成之雙層結構時之原子力顯微鏡成像，右側插圖則為左圖中對應之高度線。 134 圖 A.5堆疊前之（a）封裝層六方晶氮化硼（b）二硫化鎢（c）緩衝層六方晶氮化硼。（d）完成之三明治結構二硫化鎢電晶體 135 圖 A.6 三明治結構二硫化鎢電晶體之原子力顯微鏡成像，右側插圖則為左圖中對應之高度線。 136 圖 A.7 三明治結構二硫化鎢電晶體之堆疊過程，圖片中之十字對齊標誌長寬均為10 μm。（a）二硫化鎢堆疊於六方晶氮化硼緩衝層時，其中較小之晶體為二硫化鎢（b）沉積完金屬電極後（c）用以作為封裝層之六方晶氮化硼（d）完成堆疊之三明治結構二硫化鎢電晶體 137 圖 A.8 三明治結構二硫化鎢電晶體於未堆疊完成之雙層結構時之原子力顯微鏡成像，右側插圖則為左圖中對應之高度線。 138 圖 A.9 不同結構下的二硫化鎢電晶體之變溫轉換特性曲線，左圖之縱軸為對數尺度，右圖之縱軸為線性尺度，分別為（a）二硫化鎢單層結構（b）二硫化鎢/六方晶氮化硼雙層結構（c）六方晶氮化硼/二硫化鎢/六方晶氮化硼三明治結構 139 圖 A.10 元件#6：左上圖為元件於OM下之影像。其它圖則為其轉換特性曲線。圖片標題中之數字代表所使用之汲極-源極，例如右上圖之汲極為6號電極，源極為11號電極。 142 圖 A.11 元件#7：左上圖為元件於OM下之影像。其它圖則為其轉換特性曲線。 143 圖 A.12 元件#8：左上圖為元件於OM下之影像。其它圖則為其轉換特性曲線。 143 圖 A.13 元件#9：左上圖為元件於OM下之影像。其它圖則為其轉換特性曲線。 144 圖 A.14 元件#10：（a）為元件於OM下之影像（b-e）則為其不同汲極偏壓下之轉換特性曲線（f）輸出特性曲線 145 圖 A.15 元件#11：左上圖為元件於OM下之影像。其它圖則為其轉換特性曲線。 146 表目錄 表 2.1 二維材料電晶體之相關文獻回顧整理 21 表 2.2 二維電晶體之蕭特基能障和接觸電阻相關文獻整理 34 表 2.3 二維電晶體之退火處理過程相關文獻整理 51 表 3.1 電晶體電流-電壓量測參數 82 表 3.2 電晶體電流-電壓變溫量測參數 83 表 3.3 電晶體第二諧波量測參數 84 表 4.1 不同結構二硫化鎢電晶體之特徵參數 104 表 4.2 於圖 4.11中不同結構之二硫化鎢電晶體在溫度5 K時之特徵參數 108 表 4.3 不同退火條件下的三層結構二硫化鎢電晶體於汲極偏壓1 V與常溫時之特徵參數表 113 表 4.4 不同退火條件下的三層結構二硫化鎢電晶體於低溫（5 K）下之特徵參數 119 表 A.1 各二維二硫化鎢電晶體之退火條件與晶體厚度表 130 表 A.2 一維金屬線接觸電極之晶體厚度與乾式蝕刻製程條件 141 | - |
| dc.language.iso | zh_TW | - |
| dc.subject | 六方晶氮化硼 | zh_TW |
| dc.subject | 二硫化鎢 | zh_TW |
| dc.subject | 非線性非交互性傳輸效應 | zh_TW |
| dc.subject | 退火處理 | zh_TW |
| dc.subject | 過渡金屬硫化物 | zh_TW |
| dc.subject | 二維電晶體 | zh_TW |
| dc.subject | two-dimensional field-effect transistor (2D FET) | en |
| dc.subject | tungsten disulfide (WS2) | en |
| dc.subject | hexagonal-boron nitride (hBN) | en |
| dc.subject | trasition metal dichalcogenides (TMDCs) | en |
| dc.subject | thermal annealing | en |
| dc.subject | non-reciprocal transport effect (NRTE) | en |
| dc.title | 二維二硫化鎢電晶體之研究 | zh_TW |
| dc.title | Investigation of Two-Dimensional WS2 Field-Effect Transistors | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 110-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 陳建彰 | zh_TW |
| dc.contributor.oralexamcommittee | Wei-Li Lee;Yu-Chiang Chao;Jian-Zhang Chen | en |
| dc.subject.keyword | 二硫化鎢,六方晶氮化硼,二維電晶體,過渡金屬硫化物,退火處理,非線性非交互性傳輸效應, | zh_TW |
| dc.subject.keyword | two-dimensional field-effect transistor (2D FET),tungsten disulfide (WS2),hexagonal-boron nitride (hBN),trasition metal dichalcogenides (TMDCs),thermal annealing,non-reciprocal transport effect (NRTE), | en |
| dc.relation.page | 174 | - |
| dc.identifier.doi | 10.6342/NTU202203994 | - |
| dc.rights.note | 同意授權(全球公開) | - |
| dc.date.accepted | 2022-09-27 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 光電工程學研究所 | - |
| dc.date.embargo-lift | 2024-09-25 | - |
| 顯示於系所單位： | 光電工程學研究所 | |
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