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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/87586完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳景然 | zh_TW |
| dc.contributor.advisor | Ching-Jan Chen | en |
| dc.contributor.author | 李榕松 | zh_TW |
| dc.contributor.author | Rong-Song Li | en |
| dc.date.accessioned | 2023-06-20T16:12:43Z | - |
| dc.date.available | 2023-11-09 | - |
| dc.date.copyright | 2023-06-20 | - |
| dc.date.issued | 2022 | - |
| dc.date.submitted | 2022-11-03 | - |
| dc.identifier.citation | M. K. Song, J. Sankman, and D. Ma, “A 6 A 40 MHz four-phase ZDS hysteretic DC-DC converter with 118 mV droop and 230 ns response time for a 5 A / 5 ns load transient,” in IEEE int. Solid-State Circuits Conf. Dig. Tech. Papers, 2014, pp. 80-81.
B. Lee, M. K. Song, A. Maity, and D. B. Ma, “A 25 MHz 4-phase SAW hysteretic DC-DC converter with 1-cycle APC achieving 190 ns tsettle to 4 A load transient and above 80 % efficiency in 96.7 % of the power range,” in IEEE int. Solid-State Circuits Conf. Dig. Tech. Papers, 2017, pp. 190-191. Y. Ahn, I. Jeon and J. Roh, “A multiphase buck converter with a rotating phase-shedding scheme for efficient light-load control,” IEEE J. of Solid-State Circuits, vol. 49, no. 11, pp. 2673-2683, Nov. 2014. Y. W. Huang, T. H. Kuo, S. Y. Huang and K. Y. Fang, “A four-phase buck converter with capacitor-current-sensor calibration for load-transient-response optimization that reduces undershoot/overshoot and shortens settling time to near their theoretical limits,” IEEE J. of Solid-State Circuits, vol. 53, no. 2, pp. 552-568, Feb. 2018. Maxim Integrated, Sunnyvale, CA. MAX77812 Data Sheet. Accessed: Dec. 2020. [Online]. Available: https://datasheets.maximintegrated.com/en/ds/MAX77812.pdf C. Huang, and P. K. T. Mok, “An 82.4 % efficiency package-bondwire-based four-phase fully integrated buck converter with flying capacitor for area reduction,” in IEEE int. Solid-State Circuits Conf. Dig. Tech. Papers, 2013, pp. 362-363. H. P. Forghani-Zadeh and G. A. Rincon-Mora, “Current-sensing techniques for DC-DC converters,” in The 2002 45th Midwest Symposium on Circuits and Systems, 2002, vol. 2, pp. II-II. F. F. Ma, W. Z. Chen and J. C. Wu, “A monolithic current-mode buck converter with advanced control and protection circuits,” IEEE Trans. Power Electron., vol. 22, no. 5, pp. 1836-1846, Sep. 2007. C. F. Lee and P. K. T. Mok, “A monolithic current-mode CMOS DC-DC converter with on-chip current-sensing technique,” IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 3-14, Jan. 2004. J. J. Chen, Y. S. Hwang, Y. Ku, Y. H. Li and J. A. Chen, “A current-mode-hysteretic buck converter with constant-frequency-controlled and new active-current-sensing techniques,” IEEE Trans. Power Electron., vol. 36, no. 3, pp. 3126-3134, Mar. 2021. W. Huang, “A new control for multi-phase buck converter with fast transient response,” in Proc. 16th Annu. IEEE Appl. Power Electron. Conf. Expo., 2001, pp. 273–279. P.-H. Liu, F. C. Lee, and Q. Li, ‘‘Hybrid interleaving with adaptive PLL loop for adaptive on-time controlled switching converters,’’ in Proc. IEEE Energy Convers. Congr. Expo. (ECCE), Sep. 2014, pp. 4110–4117. Y. Ahn, I. Jeon and J. Roh, “A multiphase buck converter with a rotating phase-shedding scheme for efficient light-load control,” IEEE J. Solid-State Circuits, vol. 49, no. 11, pp. 2673-2683, Nov. 2014. W. Tang, F. C. Lee and R. B. Ridley, “Small-signal modeling of average current-mode control,” IEEE Trans. Power Electron., vol. 8, no. 2, pp. 112-119, Apr. 1993. C. C. Enz, E. A. Vittoz and F. Krummenacher, “A CMOS chopper amplifier,” IEEE J. of Solid-State Circuits, vol. 22, no. 3, pp. 335-342, June 1987. C. C. Enz and G. C. Temes, “Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization,” in Proceedings of the IEEE, vol. 84, no. 11, pp. 1584-1614, Nov. 1996. J. F. Witte, K. A. A. Makinwa and J. H. Huijsing, “A CMOS chopper offset-stabilized opamp,” IEEE J. of Solid-State Circuits, vol. 42, no. 7, pp. 1529-1535, July 2007. A. J. Jerri, “The shannon sampling theorem-its various extensions and applications: a tutorial review,” in Proceedings of the IEEE, vol. 65, no. 11, pp. 1565-1596, Nov. 1977. S. Jung, I. Song and J. D. Cressler, “Systematic methodology for applying Mason's signal flow graph to analysis of feedback circuits,” in 2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014, pp. 2421-2424. L. Lv, X. Zhou, Z. Qiao and Q. Li, “Inverter-based subthreshold amplifier techniques and their application in 0.3-V ΔΣ -modulators,” IEEE J. of Solid-State Circuits, vol. 54, no. 5, pp. 1436-1445, May. 2019. M. Bazes, “Two novel fully complementary self-biased CMOS differential amp-lifiers,” IEEE J. of Solid-State Circuits, vol. 26, no. 2, pp. 165-168, Feb. 1991. E. Bruun and P. Shah, “Dynamic range of low-voltage cascode current mirrors,” in Proceedings of ISCAS'95 - International Symposium on Circuits and Systems, 1995, pp. 1328-1331 vol.2. D. B. Ribner and M. A. Copeland, “Design techniques for cascoded CMOS op amps with improved PSRR and common-mode input range,” IEEE J. of Solid-State Circuits, vol. 19, no. 6, pp. 919-925, Dec. 1984. Maxim Integrated, Sunnyvale, CA. MAX77812 PCB Layout Guide. Accessed: Feb. 2019. Available: https://pdfserv.maximintegrated.com/en/an/AN6819.pdf Texas Instruments. Five steps to a great PB layout for a step-down converter. Available: https://www.ti.com/lit/an/slyt614/slyt614.pdf?ts=1663673703347 H. J. Zhang, “PCB layout considerations for non-isolated switching power supplies,” Linear Technology Application Note 136, Jun. 2012. Rohm Semiconductor. PCB Layout Techniques of Buck Converter. Available: https://fscdn.rohm.com/en/products/databook/applinote/ic/power/switching_regulator/converter_pcb_layout_appli-e.pdf | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/87586 | - |
| dc.description.abstract | 此論文提出一個寬負載電流範圍帶有高效率之雙相位降壓型轉換器採用被動式斜波調變自適應導通時間控制，此控制架構會將責任週期傳入低通濾波器並產生被動式斜波，此外降壓型降轉換的輸出電壓成分也會被加入至被動斜波當中，此優點為迴路轉移函數會類似一個電流模式控制且負載電流暫態響應會被加速，然而，當負載電流減少的時候會將降壓型轉換器轉變為不連續導通模式，此控制架構將會轉變為輸出電壓夾鉗之切換頻率降低模式，降壓型轉換器的輸出電壓會被夾鉗且會直接當作調變斜波，此降壓型轉換器將會變成一個類似漣波自適應導通時間控制。
重載時，系統將會根據負載電流的大小去調整相位數目，根據上述討論，所提出的目標需要一個電感電流感測電路且帶有低感測誤差的特性，此論文所提出的被動式平均電感電流感測之斬波式誤差抵銷轉導放大器擁有低誤差感測、低功率消耗與無額外時脈的特性，此技術會被應用在相位調變與電感電流平衡。對於相位交錯來說，所提出的可預測式相位交錯結合自適應導通時間的特性，此技術的優點為電路再利用、低功率消耗、無額外時脈與低面積，根據上述的技術，所提出的被動式斜波調變自適應導通時間控制之輸出電壓夾鉗之切換頻率降低模式將會自動減少切換頻率去降低控制器的靜態電流使得在輕載時轉換效率提高，在重載時，相位調變偵測負載電流的大小去開啟奴隸相位去增加轉換效率，此電路透過上述技術達到寬負載電流範圍的雙相位降壓型轉換器。 本文所提出之雙相位降壓型轉換器採用台積電0.18μm且佔據晶片面積1.242mm2，此晶片包含功率電晶體、驅動器與控制器，雙相位降壓型轉換器操作在單相位切換頻率為6MHz且輸出電壓穩定在0.4V至1.5V從輸入電壓1.6V至2.0V而來，負載電流範圍1mA至3A內皆有80%以上的轉換效率，最高效率在負載電流為0.3A達到95.58%，當負載電流暫態響應發生的時候，兩個相位會立即打開去對輸出電壓充電，當負載電流1mA上升至3A時，輸出電壓掉落87mV，此外在最小的負載電流1mA下，控制器的靜態電流達到22.79μA。 | zh_TW |
| dc.description.abstract | A dual-phase buck converter with high efficiency loading current range using passive ramp modulation adaptive on-time control (PSRAOT control) is proposed. This control architecture will pass the duty cycle into the low-pass filter and generate the modulation ramp. In addition, the output voltage of the buck converter will also be added to the modulation ramp. The advantage is that the loop gain transfer function will be similar current mode control and the loading current transient response will be accelerated. However, when the loading current decreases to turn the buck converter into discontinuous con-duction mode (DCM), the control architecture converts to output voltage clamping with switching frequency reduction mode (OVCSFR mode). The output voltage of the buck converter will be clamped and it will be directly used as the modulation ramp. The buck converter will be a ripple-based adaptive on-time control (RBAOT control).
In the heavy loading current, the system will adjust the number of phases according to the loading current. As discussed above, the proposed target requires an inductor current sensing with a low sensing error. In this paper, the passive average inductor current sense with chopper offset cancellation Gm amplifier is proposed, which has the characteristics of low sensing error, low power consumption and external clockless. This technique will be applied to phase shedding and inductor current balance. With regard to phase interleaving, the proposed predictive phase interleaving incorporates the circuit characteristics of adaptive on-time control. This technique has the characteristics of circuit reuse, low power consumption, external clockless and low area. According to the above techniques, the proposed PSRAOT with OVCSFR mode will decrease switching frequency to reduce the quiescent current of the controller and the conversion efficiency will increase in light loading current. Phase shedding will detect the size of the loading current and it will turn on the slave phase to increase conversion efficiency in heavy loading current. The proposed dual-phase buck converter applies above techniques to achieve wide range efficiency. Fabricated in a TSMC 0.18μm CMOS process, the prototype dual-phase buck converter occupies 1.24mm2. The chip contains power MOS, driver and controller. The buck converter operates 6MHz of switching frequency at a single phase and regulates output voltage to in the range of 0.4V to 1.5V from 1.6V to 2.0V input voltage. The conversion efficiency is above 80% between the loading current range of 1mA – 3A and the maximum conversion efficiency is 95.58%. When the loading current transient occurs, the two phases can be instantly fully opened for charging output voltage. With a 1mA to 3A step in the loading current, the undershoot voltage is 87mV. In addition, the quiescent current of the controller is 22.79μA at the lightest loading current of 1mA. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2023-06-20T16:12:43Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2023-06-20T16:12:43Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 口試委員審定書 II
Acknowledgements III 中文摘要 V Abstract VII Table of Contents IX List of Figures XIII List of Tables XXIII Chapter 1 Introduction 1 1.1 Background: DC-DC Converter and PMIC for Mobile Device and Multimedia Audio-Visual Device 1 1.2 Introduction of Adaptive On-Time Control Operation 4 1.2.1 Adaptive On-Time Control Circuit Diagram 4 1.2.2 Characteristics of Adaptive On-Time Control 5 1.3 Thesis Motivation and Designed Target 8 1.3.1 Thesis Motivation 8 1.3.2 Designed Target 9 1.3.3 Advantages of High Switching Frequency 10 1.3.4 Multiphase Buck Converter Control Type Issues 11 1.3.5 Inductor Current Sense Issues 12 1.3.6 Phase Interleaving Issues 17 1.4 Thesis Outline 19 Chapter 2 Review of Multiphase Buck Converter 22 2.1 The Basic Concept of Single-Phase Buck Converter 22 2.1.1 The Steady-State Analysis of Single-Phase Buck Converter 22 2.1.2 The Steady-State Analysis of Multiphase Buck Converter 26 2.1.3 Frequency Response Analysis of Multiphase Buck Converter 28 2.1.4 Efficiency Analysis of Multiphase Buck Converter 50 2.1.5 Summary of Multiphase Buck Converter 56 2.2 Review of the Other State-of-the-Art Multiphase Buck Converter 61 2.2.1 ISSCC 2014 – ZDS Hysteretic DC-DC Converter [1] 61 2.2.2 ISSCC 2017 – SAW Hysteresis DC-DC Converter 64 Chapter 3 The Proposed Main Controller Technique for Multiphase Buck Converter 67 3.1 Architecture of The Dual-Phase Buck Converter 67 3.2 The Proposed Dual-Phase Buck Converter with Wide Range Efficiency 69 3.3 The Proposed Passive Ramp Modulation Adaptive On-Time Control (PSRAOT Control) 71 3.3.1 Passive Ramp Modulation Architecture 72 3.3.2 The Conventional Constant On-Time Control 74 3.3.3 The Adaptive On-Time Control 76 3.3.4 The Loop Gain Analysis of the PSRAOT Control 78 3.4 Single-Phase Architecture of PSRAOT Control with OVCSFR Mode 86 3.4.1 PSRAOT Control with OVCSFR Mode in CCM 86 3.4.2 PSRAOT Control with OVCSFR Mode in DCM 88 3.5 The Proposed Passive Average Inductor Current Sense with Chopper Offset Cancellation Gm Amplifier 94 3.5.1 The Circuit Architecture of the Passive Average Inductor Current Sense with Chopper Offset Cancellation Gm Amplifier 94 3.5.2 The Architecture of the Phase Shedding 101 3.5.3 The Architecture of the Inductor Current Balance 104 3.6 The Proposed Predictive Phase Interleaving 107 3.7 The Proposed Loading Current Transient Response Accelerator 110 3.8 Summary 112 Chapter 4 The Proposed Sub-Circuit in Main Controller Techniques 113 4.1 Zero Current Detector with Protection 113 4.2 Low Power Circuit Techniques 115 4.2.1 The Floating Gate Technique 115 4.2.2 The Voltage Controlled Current Source (VCCS) with The Floating Gate Technique 116 4.2.3 Summary 118 4.3 Error Amplifier with Clamping Mechanism 118 4.3.1 The Circuit Architecture of the Error Amplifier 118 4.3.2 The Loading Effect Analysis of the Error Amplifier 119 4.3.3 The Two-Stage OPAMP of the Error Amplifier 123 4.3.4 Summary 126 4.4 Inverter-Base Comparator 128 4.5 Wide Swing Cascode Current Mirror 131 4.5.1 The Issue of Conventional Current Mirror 131 4.5.2 The Advantages of Wide Swing Cascode Current Mirror 132 4.6 Chopper Offset Cancellation Gm Amplifier with Super Source Follower 134 4.6.1 The Issue of Differential Source Follower 134 4.6.2 Differential Super Source Follower 136 4.6.3 The Circuit of Chopper Offset Cancellation Gm Amplifier with Super Source Follower 136 Chapter 5 Simulation and Experimental Results 139 5.1 The Dual-Phase Buck Converter Chip Fabrication Version I 139 5.1.1 Full Transistor Level Layout and Chip Die Photo Version I 139 5.1.2 Chip Bonding Diagram Version I 141 5.2 The Dual-Phase Buck Converter Chip Fabrication Version II 143 5.2.1 Full Transistor Level Layout and Chip Die Photo Version II 143 5.2.2 Chip Bonding Diagram Version II 146 5.3 Printed Circuit Board Design Considerations 148 5.4 Measurement Setup 153 5.5 Simulated and Experimental Results 155 5.5.1 Simulation Results 155 5.5.2 Measurement Results 161 Chapter 6 Conclusions and Future Works 167 6.1 Conclusions 167 6.2 Future Works 167 Reference 168 | - |
| dc.language.iso | en | - |
| dc.subject | 被動式斜波調變 | zh_TW |
| dc.subject | 可預測式相位交錯 | zh_TW |
| dc.subject | 被動式電感電流感測 | zh_TW |
| dc.subject | 多相位降壓型轉換器 | zh_TW |
| dc.subject | multiphase buck converter | en |
| dc.subject | passive average inductor current sense | en |
| dc.subject | predictive phase interleaving | en |
| dc.subject | passive ramp modulation | en |
| dc.title | 一毫安培至三安培間效率80%之雙相位自適應導通時間降壓型轉換器採用被動式斜坡調變與電流感測技術 | zh_TW |
| dc.title | A 1mA to 3A 80% Efficiency Dual-Phase Adaptive On-Time Control Buck Converter with Passive Ramp Modulation and Current Sensing Technique | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 111-1 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 陳耀銘;林宗賢;黃育賢 | zh_TW |
| dc.contributor.oralexamcommittee | Yaow-Ming Chen;Tsung-Hsien Lin;Yuh-Shyan Hwang | en |
| dc.subject.keyword | 多相位降壓型轉換器,被動式電感電流感測,可預測式相位交錯,被動式斜波調變, | zh_TW |
| dc.subject.keyword | multiphase buck converter,passive average inductor current sense,predictive phase interleaving,passive ramp modulation, | en |
| dc.relation.page | 171 | - |
| dc.identifier.doi | 10.6342/NTU202210005 | - |
| dc.rights.note | 同意授權(限校園內公開) | - |
| dc.date.accepted | 2022-11-03 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| dc.date.embargo-lift | 2027-10-24 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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