請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/86465完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳信樹(Hsin-Shu Chen) | |
| dc.contributor.author | Ming-Wei Kung | en |
| dc.contributor.author | 龔明緯 | zh_TW |
| dc.date.accessioned | 2023-03-19T23:57:24Z | - |
| dc.date.copyright | 2022-08-22 | |
| dc.date.issued | 2022 | |
| dc.date.submitted | 2022-08-17 | |
| dc.identifier.citation | [ 1 ] A. G. Venon, Y. Dupuis, P. Vasseur and P. Merriaux, 'Millimeter Wave FMCW RADARs for perception, recognition and localization in automotive applications: A survey,' in IEEE Transactions on Intelligent Vehicles [ 2 ] R. Ciocoveanu and V. Issakov, 'Low-Power 60GHz Receiver with an Integrated Analog Baseband for FMCW Radar Applications in 28nm CMOS Technology,' 2021 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2021, pp. 4-6. [ 3 ] TI AWR1642 Single-Chip 77- and 79-GHz FMCW Radar sensor data sheet [ 4 ] Shanthi Pavan; Richard Schreier; Gabor C. Temes, 'High‐Order Delta‐Sigma Modulators,' in Understanding Delta-Sigma Data Converters , IEEE, 2017, pp.83-116. [ 5 ] B. Wu, S. Zhu, B. Xu, and Y. Chiu, “A 24.7 mW 65 nm CMOS SAR-Assisted CT Delta-Sigma Modulator With Second-Order Noise Coupling Achieving 45 MHz Bandwidth and 75.3 dB SNDR,” IEEE Journal of Solid-State Circuits, vol. 51, no. 12, pp. 2893–2905, Dec. 2016. [ 6 ] T. Lo, C. Weng, H. Hsieh, Y. Shu, and P. Chiu, “20.4 An 8 × - OSR 25MHz-BW 79.4dB/74dB DR/SNDR CT Δ σ Modulator Using 7b Linearized Segmented DACs with Digital Noise-Coupling-Compensation Filter in 7nm FinFET CMOS,” in 2019 IEEE International Solid-State Circuits Conference - (ISSCC), Feb. 2019, pp. 334–336. [ 7 ] Jose M. de la Rosa, 'Practical Realization of ΣΔMs: From Circuits to Chips,' in Sigma-Delta Converters: Practical Design Guide, IEEE, 2018, pp.341-387 [ 8 ] K. Lee, M. Bonu, and G. C. Temes, “Noise-coupled Delta Sigma ADC’s,” Electronics Letters, vol. 42, no. 24, pp. 1381–1382, Nov. 2006. [ 9 ] K. Lee, M. R. Miller, and G. C. Temes, “An 8.1 mW, 82 dB Delta-Sigma ADC With 1.9 MHz BW and -98 dB THD,” IEEE Journal of Solid-State Circuits, vol. 44, no. 8, pp. 2202–2211, Aug. 2009. [ 10 ] Y. Wang and G. C. Temes, “Noise-coupled continuous-time delta-sigma ADCs,” Electronics Letters, vol. 45, no. 6, pp. 302–303, Mar. 2009 [ 11 ] L. He et al., 'Digital Noise-Coupling Technique for Delta–Sigma Modulators With Segmented Quantization,' in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 61, no. 6, pp. 403-407, June 2014 [ 12 ] Y. H. Leow, H. Tang, Z. C. Sun, and L. Siek, “A 1 V 103 dB 3rd-Order Audio Continuous-Time-Delta-Sigma ADC With Enhanced Noise Shaping in 65 nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 51, no. 11, pp. 2625–2638, Nov. 2016. [ 13 ] I. -H. Jang et al., 'A 4.2mW 10MHz BW 74.4dB SNDR fourth-order CT DSM with second-order digital noise coupling utilizing an 8b SAR ADC,' 2017 Symposium on VLSI Circuits, 2017, pp. C34-C35. [ 14 ] S. -H. Wu, Y. -S. Shu, A. Y. -C. Chiou, W. -H. Huang, Z. -X. Chen and H. -Y. Hsieh, '9.1 A Current-Sensing Front-End Realized by A Continuous-Time Incremental ADC with 12b SAR Quantizer and Reset-Then-Open Resistive DAC Achieving 140dB DR and 8ppm INL at 4kS/s,' 2020 IEEE International Solid-State Circuits Conference - (ISSCC), 2020, pp. 154-156. [ 15 ] S. Li, B. Qiao, M. Gandara, D. Z. Pan and N. Sun, 'A 13-ENOB Second-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using the Error-Feedback Structure,' in IEEE Journal of Solid-State Circuits, vol. 53, no. 12, pp. 3484-3496, Dec. 2018 [ 16 ] J. Liu, S. Li, W. Guo, G. Wen, and N. Sun, “A 0.029-mm2 17-fJ/Conversion-Step Third-Order CT ΔΣ ADC With a Single OTA and Second-Order Noise-Shaping SAR Quantizer,” IEEE Journal of Solid-State Circuits, vol. 54, no. 2, pp. 428–440, Feb. 2019. [ 17 ] G. Wei, P. Shettigar, F. Su, X. Yu and T. Kwan, “A 13-ENOB, 5 MHz BW, 3.16 mW multi-bit continuous-time ΔΣ ADC in 28 nm CMOS with excess-loop-delay compensation embedded in SAR quantizer, ” 2015 Symposium on VLSI Circuits (VLSI Circuits), Kyoto, 2015, pp. C292-C293 [ 18 ] Y. Zhong et al., 'A Second-Order Purely VCO-Based CT ΔΣ ADC Using a Modified DPLL Structure in 40-nm CMOS,' in IEEE Journal of Solid-State Circuits, vol. 55, no. 2, pp. 356-368, Feb. 2020. [ 19 ] S. Li, D. Z. Pan and N. Sun, “An OTA-Less Second-Order VCO-Based CT ΔΣ Modulator Using an Inherent Passive Integrator and Capacitive Feedback, ” IEEE Journal of Solid-State Circuits, vol. 55, no. 5, pp. 1337-1350, May 2020. [ 20 ] J. L. A. de Melo, J. Goes and N. Paulino, 'A 0.7 V 256 μW ΔΣ modulator with passive RC integrators achieving 76 dB DR in 2 MHz BW,' 2015 Symposium on VLSI Circuits (VLSI Circuits), Kyoto, 2015, pp. C290-C291. [ 21 ] M. Keller, A. Buhmann, J. Sauerbrey, M. Ortmanns and Y. Manoli, 'A Comparative Study on Excess-Loop-Delay Compensation Techniques for Continuous-Time Sigma–Delta Modulators,' in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 55, no. 11, pp. 3480-3487, Dec. 2008. [ 22 ] L. Dorrer, F. Kuttner, P. Greco, P. Torta and T. Hartig, 'A 3-mW 74-dB SNR 2-MHz continuous-time delta-sigma ADC with a tracking ADC quantizer in 0.13-um CMOS,' in IEEE Journal of Solid-State Circuits, vol. 40, no. 12, pp. 2416-2427, Dec. 2005. [ 23 ] B. K. Thandri and J. Silva-Martinez, 'A robust feedforward compensation scheme for multistage operational transconductance amplifiers with no Miller capacitors,' in IEEE Journal of Solid-State Circuits, vol. 38, no. 2, pp. 237-243, Feb. 2003. [ 24 ] B. Nauta, “A CMOS transconductance-C filter technique for very high frequencies,” IEEE Journal of Solid-State Circuits, vol. 27, no.2, Art. no. 2, Feb. 1992 [ 25 ] Y. Chae and G. Han, 'Low Voltage, Low Power, Inverter-Based Switched-Capacitor Delta-Sigma Modulator,' in IEEE Journal of Solid-State Circuits, vol. 44, no. 2, pp. 458-472, Feb. 2009 [ 26 ] A. Ismail and I. Mostafa, 'A Process-Tolerant, Low-Voltage, Inverter-Based OTA for Continuous-Time-Sigma-Delta ADC,' in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 9, pp. 2911-2917, Sept. 2016. [ 27 ] L. Lv, X. Zhou, Z. Qiao and Q. Li, 'Inverter-Based Subthreshold Amplifier Techniques and Their Application in 0.3-V ΔΣ-Modulators,' in IEEE Journal of Solid-State Circuits, vol. 54, no. 5, pp. 1436-1445, May 2019. [ 28 ] R. G. Carvajal et al., 'The flipped voltage follower: a useful cell for low-voltage low-power circuit design,' in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 52, no. 7, pp. 1276-1291, July 2005 [ 29 ] T. Y. Man, K. N. Leung, C. Y. Leung, P. K. T. Mok and M. Chan, 'Development of Single-Transistor-Control LDO Based on Flipped Voltage Follower for SoC,' in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 55, no. 5, pp. 1392-1401, June 2008 [ 30 ] P. Hazucha, T. Karnik, B. A. Bloechel, C. Parsons, D. Finan and S. Borkar, 'Area-efficient linear regulator with ultra-fast load regulation,' in IEEE Journal of Solid-State Circuits, vol. 40, no. 4, pp. 933-940, April 2005 [ 31 ] P. R. Surkanti, A. Garimella and P. M. Furth, 'Flipped Voltage Follower Based Low Dropout (LDO) Voltage Regulators: A Tutorial Overview,' 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID), 2018, pp. 232-237 [ 32 ] C. -Y. Ho, C. Liu, C. -L. Lo, H. -C. Tsai, T. -C. Wang and Y. -H. Lin, '15.2 A 4.5mW CT self-coupled ΔΣ modulator with 2.2MHz BW and 90.4dB SNDR using residual ELD compensation,' 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers, 2015, pp. 1-3 [ 33 ] W. Shi et al., '10.4 A 3.7mW 12.5MHz 81dB-SNDR 4th-Order CTDSM with Single-OTA and 2nd-Order NS-SAR,' 2021 IEEE International Solid-State Circuits Conference (ISSCC), 2021, pp. 170-172 [ 34 ] S. Pavan, 'Excess Loop Delay Compensation in Continuous-Time Delta-Sigma Modulators,' in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 55, no. 11, pp. 1119-1123, Nov. 2008 [ 35 ] T. Nandi, K. Boominathan and S. Pavan, 'Continuous-Time Delta-Sigma Modulators With Improved Linearity and Reduced Clock Jitter Sensitivity Using the Switched-Capacitor Return-to-Zero DAC,' in IEEE Journal of Solid-State Circuits, vol. 48, no. 8, pp. 1795-1805, Aug. 2013 | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/86465 | - |
| dc.description.abstract | 近期,使用頻率調變連續波雷達來做物件的偵測變得十分熱門,而基頻電路中類比數位轉換器的頻寬跟可以偵測物件的距離是呈正相關的,使用高頻寬的類比數位轉換器可以增加偵測到的距離亦或是減低整體的功耗,因此一個低過取樣率的連續時間三角積分器通常會被用於此應用。 本論文提出兩個一點二五百萬赫頻寬的連續時間型三角積分類比數位轉換器,使用連續離散混和的架構而不是用傳統高階的做法來實現四階的迴路濾波器,兩階使用傳統的迴路,兩階使用數位噪聲耦合之技巧,可以省下兩個運算轉導放大器的功耗;在量化器的選擇上使用了八位元的連續漸進式類比數位轉換器(SAR ADC),並且重複利用了它的電容陣列來完成噪聲耦合。在傳統迴路上,在第一個作品中,使用了混合米勒與前饋補償的雙級運算放大器 ; 而第二個作品中,則使用了高功耗效率基於反向器的運算轉導放大器(Inverter-based OTA),並且為了解決在製程與溫度上的變異,提出了一個自動調節電壓的低壓降線性穩壓器,在不同情況下,都可以使此基於反向器的運算轉導放大器有穩定的小訊號表現,並且連續時間三角積分器的解析度都大於70 dB。 此晶片透過台積電TSMC 28 nm CMOS RF High Performance Compact Mobile Computing Plus (HPC+) ELK Cu 1P10M實現,在四十百萬赫茲的取樣頻率下操作,於一點二五百萬赫茲的頻寬下,第一個作品量測到的最大訊號對雜訊與失真比為75 dB,動態範圍為82 dB,整體功耗為0.8 mW,Schreier品質因數為167 dB ; 而第二個作品量測到的最大訊號對雜訊與失真比為69.52 dB,動態範圍為69.2 dB,整體功耗為0.4 mW,Schreier品質因數為164.5 dB | zh_TW |
| dc.description.abstract | Recently, the FMCW radar has been very popular in object detection. The bandwidth of the baseband ADC is related to the object observation range. The ADC with higher bandwidth can either increase the range or reduce the power consumption. Therefore, a low-OSR CTDSM is usually used in this application. This thesis presents two CTDSM ADCs with a bandwidth of 1.25MHz. Instead of using the traditional high-order loop filter, it uses a CT-DT hybrid architecture to implement a 4th-order loop filter. 2nd-order is implemented in a traditional method, and the other 2nd-order is implemented by the digital noise couple (DNC). It can reduce power consumption by saving two OTAs. The quantizer is chosen to use 8-bit SAR ADC, and its capacitor array is reused for DNC. In the loop filter, the first work uses the two-stage OTA with miller and feedforward compensation, and the second work uses a high power efficiency inverter-based OTA. An LDO that can automatically adjust the supply voltage is proposed to solve the PVT variation. The inverter-based OTA can have stable small-signal performance, and the CTDSM has more than 70 dB over PVT. Two chips are implemented by TSMC 28 nm CMOS RF High Performance Compact Mobile Computing Plus (HPC+) ELK Cu 1P10M. The prototype modulator is operated at 40MHz. The first work achieves a peak SNDR of 75 dB and 82 dB dynamic range (DR) over 1.25MHz. The overall power consumption is 0.8 mW, and the FoMs is 167 dB. The second work achieves a peak SNDR of 69.52 dB and 69.2 dB DR. The overall power consumption is 0.4 mW, and the FoMs is 164.5 dB. | en |
| dc.description.provenance | Made available in DSpace on 2023-03-19T23:57:24Z (GMT). No. of bitstreams: 1 U0001-1508202213470300.pdf: 9155401 bytes, checksum: 0d7deec58e30ae900d536edb6a037b5d (MD5) Previous issue date: 2022 | en |
| dc.description.tableofcontents | 口試委員會審定書 i 致謝 iii 摘要 v Abstract vi Contents vii List of Figures xii List of Tables xvii Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 6 Chapter 2 Fundamentals of Delta-Sigma Modulators 7 2.1 Introduction 7 2.1.1 Sampling and Quantization 8 2.1.2 Oversampling 10 2.1.3 Noise Shaping Technique 13 2.1.4 ADC Performance Metrics 14 2.1.4.1 Signal-to-Noise Ratio (SNR) 14 2.1.4.2 Signal-to-Noise and Distortion Ratio (SNDR) 15 2.1.4.3 Spurious-Free Dynamic Range (SFDR) 15 2.1.4.4 Dynamic Range (DR) 15 2.1.4.5 Effective Number of Bits (ENOB) 16 2.1.4.6 Figure of Merit (FoM) 16 2.2 Delta-Sigma Modulator Topologies 17 2.2.1 Discrete-Time Delta-Sigma Modulator (DTDSM) 17 2.2.2 Continuous-Time Delta-Sigma Modulator (CTDSM) 19 2.2.2.1 Time-Constant Variations 19 2.2.2.2 Excess Loop Delay 21 2.2.2.3 DAC Nonlinearity 22 2.2.2.4 Clock Jitter 22 2.2.2.5 OTA Non-ideality 23 2.2.3 Comparison of CT and DT DSM 24 2.2.4 Comparison of Single-Bit and Multi-Bit DSM 25 2.3 Loop Filter Topologies 26 2.3.1 Feedback Topology 27 2.3.2 Feedforward Topology 29 2.3.3 Combination of Feedforward and Feedback Topology 30 2.4 Multi-stage Delta-Sigma Modulator 31 2.4.1 Multi-Stage Noise-Shaping Modulator (MASH) 31 2.4.2 Sturdy-MASH Architecture 33 2.4.3 Noise-Coupled Architecture 34 2.5 Summary 35 Chapter 3 Behavior simulation and Analysis of the proposed 4th-order CTDSM with PVT-insensitive Inverter-based OTAs 36 3.1 Introduction 36 3.2 Systematic Design 36 3.2.1 Design Goal 37 3.2.2 Structure Comparison and Analysis 37 3.2.3 DSM Realization 41 3.2.3.1 NTF design 41 3.2.3.2 Loop filter realization 43 3.2.3.3 Quantizer realization 45 3.2.3.4 Excess Loop Delay Compensation (ELDC) 46 3.2.4 Overall Performance 49 3.2.4.1 Signal-to-Quantization-Noise Ratio (SQNR) 50 3.2.4.2 Dynamic Range (DR) 51 3.2.4.3 Signal Transfer Function (STF) 51 3.3 Modification for the real circuit implementation 52 3.3.1 Digital Noise couple implementation 52 3.3.2 ELDC real implementation 53 3.4 Real Component Realization and Results 55 3.5 Effect of Time-constant variation 57 3.6 Effect of DAC Nonlinearity 58 3.7 Effect of Clock Jitter 62 3.8 Effect of OTA Non-ideality 63 3.8.1 Finite DC gain 64 3.8.2 Finite Unity-Gain-Bandwidth (UGB) 64 3.9 Summary 65 Chapter 4 Circuit Implementation of the proposed 4th-order CTDSM with PVT-insensitive Inverter-based OTAs 67 4.1 Introduction 67 4.2 Proposed Architecture 67 4.2.1 Chip 1 (with FF-Miller compensation OTA and RZ DAC) 68 4.2.2 Chip 2 (with inverter-based OTA and NRZ DAC) 69 4.3 Circuit Implementations 70 4.3.1 CT Loop Filter 70 4.3.1.1 RC Tuning 71 4.3.1.2 Miller and feedforward hybrid compensation OTA (Chip 1) 73 4.3.1.3 Proposed Inverter-based OTA 74 4.3.1.4 Proposed LDO for Inverter-based OTA 76 4.3.2 ASAR Quantizer 82 4.3.2.1 ASAR Architecture 82 4.3.2.2 CDAC Multi-Mode Control 84 4.3.3 DNC Circuit 85 4.3.4 Main Loop DAC 86 4.3.5 ELDC DAC 89 4.4 Simulation Results 90 4.4.1 Post simulation 90 4.4.1.1 Chip 1 90 4.4.1.2 Chip 2 92 4.4.2 Noise analysis 94 4.4.3 PVT simulation of Chip 2 96 Chapter 5 Experimental Results 98 5.1 Measurement Environment 98 5.2 Measurement Results 99 5.2.1 Chip 1 (with class-A OTA) measurement results 100 5.2.2 Chip 2 (with Inverter-based OTA) measurement results 104 5.3 Comparison 111 Chapter 6 Conclusions and Future work 114 6.1 Conclusions 114 6.2 Future work 114 Bibliography 116 | |
| dc.language.iso | en | |
| dc.subject | 數位噪聲耦合 | zh_TW |
| dc.subject | 基於反向器的運算轉導放大器 | zh_TW |
| dc.subject | 低功耗 | zh_TW |
| dc.subject | 連續時間型三角積分調變器 | zh_TW |
| dc.subject | 類比數位轉換器 | zh_TW |
| dc.subject | 基於反向器的運算轉導放大器 | zh_TW |
| dc.subject | 數位噪聲耦合 | zh_TW |
| dc.subject | 摺疊電壓隨耦器 | zh_TW |
| dc.subject | 連續時間型三角積分調變器 | zh_TW |
| dc.subject | 低壓降線性穩壓器 | zh_TW |
| dc.subject | 類比數位轉換器 | zh_TW |
| dc.subject | 低壓降線性穩壓器 | zh_TW |
| dc.subject | 低功耗 | zh_TW |
| dc.subject | 摺疊電壓隨耦器 | zh_TW |
| dc.subject | inverter-based OTA | en |
| dc.subject | analog-to-digital converter | en |
| dc.subject | continuous-time delta-sigma modulator | en |
| dc.subject | low power | en |
| dc.subject | digital noise couple | en |
| dc.subject | FVF | en |
| dc.subject | LDO | en |
| dc.subject | analog-to-digital converter | en |
| dc.subject | continuous-time delta-sigma modulator | en |
| dc.subject | low power | en |
| dc.subject | inverter-based OTA | en |
| dc.subject | digital noise couple | en |
| dc.subject | FVF | en |
| dc.subject | LDO | en |
| dc.title | 一個四階的連續時間型三角積分類比數位轉換器使用製程電壓溫度不敏感基於反向器的運算轉導放大器與數位噪聲耦合之技巧 | zh_TW |
| dc.title | A 4th-order Continuous-Time Delta-Sigma Modulator ADC using PVT-insensitive Inverter-based OTA and Digital Noise Couple Technique | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 110-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 林宗賢(Tsung-Hsien Lin),陳佳宏(Chia-Hung Chen),許雲翔(Yun-Shiang Shu) | |
| dc.subject.keyword | 類比數位轉換器,連續時間型三角積分調變器,低功耗,基於反向器的運算轉導放大器,數位噪聲耦合,摺疊電壓隨耦器,低壓降線性穩壓器, | zh_TW |
| dc.subject.keyword | analog-to-digital converter,continuous-time delta-sigma modulator,low power,inverter-based OTA,digital noise couple,FVF,LDO, | en |
| dc.relation.page | 120 | |
| dc.identifier.doi | 10.6342/NTU202202401 | |
| dc.rights.note | 同意授權(全球公開) | |
| dc.date.accepted | 2022-08-17 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| dc.date.embargo-lift | 2022-08-22 | - |
| 顯示於系所單位: | 電子工程學研究所 | |
文件中的檔案:
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| U0001-1508202213470300.pdf | 8.94 MB | Adobe PDF | 檢視/開啟 |
系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。
