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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/8567完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 郭正邦 | |
| dc.contributor.author | Chia-Hsing Chen | en |
| dc.contributor.author | 陳嘉興 | zh_TW |
| dc.date.accessioned | 2021-05-20T19:58:31Z | - |
| dc.date.available | 2015-07-15 | |
| dc.date.available | 2021-05-20T19:58:31Z | - |
| dc.date.copyright | 2010-07-15 | |
| dc.date.issued | 2010 | |
| dc.date.submitted | 2010-07-15 | |
| dc.identifier.citation | [1]A.O. Adan, T. Naka, A. Kagisawa, and H. Shimizu, “SOI as Mainstream IC Technology, “ SOI Conf. Dig., 9-12, 1998.
[2]K. F. Goser, C. Pacha, A. Kanstein, and M. L. Rossmann, “Aspects of Systems and Circuits for Nanoelectronics, “ Proc. Of IEEE, 85(4), 558-576, 1997. [3]S. S. Chen and J. B. Kuo, “An Analytical CAD Kink Effect Model of Partially-Depleted SOI NMOS Devices Operating in Strong Inversion,” Solid State Electronics, Vol. 41, No. 3, pp. 447-458, March 1997. [4]J. B. Kuo, “Low-Voltage SOI CMOS Devices and Circuits,” Wiley, New York, 2001. [5] H. J. Hung, J. B. Kuo, D. Chen, C. T. Tsai an C. S. Yeh, ”Shallow Trench Isolation-Related Narrow Channel Effect on the Kink Effect Behavior of 40nm PD SOI NMOS Device, ”Solid State Electronics, Vol. 54, No. 1, Jan. 2010 [6]David K. Cheng 'Field and wave electromagnetics , 'Pearson,1989 [7]K.Kumagai, H.Iwaki, A.Yoshino and S.Kurosawa, 'A 3D Analysis of Source/Drain Capacitance in SOI MOSFET for Practical Circuit Design,' IEEE SOI Conf. Proc. pp. 15-16, Oct. 1994. [8]Taurus Medici User Guide, Synopsys Inc., Mountain View, CA, 144 Oct. 2005. [9] D. E. Ward and R. W. Dutton,“A Charge-Oriented Model for MOS Transistor Capacitances,” IEEE J. Solid-State Circuits, Vol.13,p.703-708, Oct 1978. [10]J. B. Kuo et al., “Analytical bandgap-narrowing-related current-gain model for BJT devices operating at 77 K,” Solid State Electron., vol. 35, no. 6, pp. 785–790, Jun. 1992. [11]K. W. Su and J. B. Kuo, “A Non-Local Impact Ionization/Lattice Temperature Model for VLSI Double-Gate Ultrathin SOI NMOS Devices,” IEEE Trans.Electron Devices, Vol. 44, No. 2, pp. 324-330,Feb.1997. [12]I. S. Lin, J. B. Kuo, D. Chen, C. S. Yeh, and C. T.Tsai, “STI-induced mechanical stress-related Kink effect of 40nm PD SOI NMOS devices,”EIROSOI, pp. 81-82,Cork, Jan. 2008. [13]J. Y. Choi, J. G. Fossum, “Analysis and Control of Floating-Body Bipolar Effects in Fully Depleted Submicormeter SOI MOSFET’S,” IEEE Trans. Electron Devices, Vol. 38, pp. 1384-1391, 1991. [14]Quyang Q, Cai J, Ning T H and Johnson J B 2002 ‘’A simulation study on thin SOI bipolar transistors with fully or partially depleted collector,’’ IEEE BCTM. 1 28–31 [15]Cai J and Ning T H 2004 Bipolar transistor on thin SOI:concept, status and prospect Proc. of IEEE Int. Conf. on Solid State and IC Technology pp 2102–7 [16]E. V. Ploeg, C.T. Nguyen, S. S. Wong and J. D. Plummer, “Parasitic Bipolar Gain in Fully Depleted n-Channel SOI MOSFET’S,” IEEE Trans. Electron Devices, Vol. 41, pp. 970-977, 1994. [17] N. Weste and D. Harris,’’ CMOS VLSI Design, A Circuits and Systems Perspective,’’ 3rd Ed., Addison-Wesley, 2005. [18] YG Chen, JB Kuo, Z Yu, RW Dutton,’’An analytical drain current model for short-channel fully-depleted ultrathin silicon-on-insulator NMOS devices,’’ Solid-State Electronics, 1995 [19] ITRS, http://www.itrs.net1Common/2007Update/2007Update.htm. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/8567 | - |
| dc.description.abstract | 在本論文中，描述使用40 奈米部份解離絕緣體上矽金氧半元件在不同頻率下之導通與關閉的暫態分析
第一章中介紹絕緣體上矽金氧半(SOI)元件及其元件特性，並對部分解離絕緣體上矽金氧半元件(PDSOI)進行探討。 在第二章將建立一個適用於暫態分析的等效電路模型，在更高的上升時間下，汲極電流會因內部寄生雙載子電晶體之電流增益增大而變，較小的位移電流與實驗數據可以驗證。 在第三章將討論在不同的下降時間下，部分解離絕緣體上矽金氧半元件之其暫態的分析。在更高的下降時間下內部寄生雙載子電晶體之M-1 會相對變小，藉由模擬元件內部載子分佈情形，當操作頻率降低，撞擊游離效應將不明顯。 第四章為論文總結與未來工作 | zh_TW |
| dc.description.abstract | This thesis reports modeling the parasitic bipolar device in the 40nm PD SOI NMOS device considering the floating body effect. Using a unique extraction method, the function of the parasitic bipolar device during DC and transient operations could be modeled.
During the turn-on transient by imposing a step voltage from 0V to 2V at the gate, the case with a slower rise time shows a faster turn-on in the drain current due to a stronger function of the parasitic bipolar device from smaller displacement currents through the gate oxide, as reflected in the current gain, as verified by the experimentally measured results. During the turn-off transient by imposing a step voltage from 2V to 0V at the gate, the case with a faster fall time shows a faster turn-off in the drain current due to a stronger function of the parasitic bipolar device. With a slower fall time shows a bigger multiplication factor imply stronger impact ionization , Verified by the experimentally measured data and the 2D simulation results, Chapter 4 is conclusion and future work. | en |
| dc.description.provenance | Made available in DSpace on 2021-05-20T19:58:31Z (GMT). No. of bitstreams: 1 ntu-99-R97943084-1.pdf: 3455445 bytes, checksum: f817c76fbcc41da6c3d967b7e0673f39 (MD5) Previous issue date: 2010 | en |
| dc.description.tableofcontents | 口試委員會審定書 i
誌謝 iii 中文摘要 iv 英文摘要 v Chapter 1 導論 1 1.1 絕緣體上矽金氧半元件(silicon on isulator；SOI CMOS)簡介 2 1.2 部分解離絕緣體上矽金氧半元件(PDSOI) 3 1.3 電流傳導機制(Current Conduction Mechanism) 5 1.4 論文架構 6 Chapter 2 部分解離絕緣體上矽N 型金氧半元件之turn-on 暫態分析 7 2.1 考慮撞擊游離(impact ionization)之汲極電流模型 8 2.1.1 元件架構 8 2.1.2 直流分析 9 2.1.3 汲極電流模型 10 2.2 暫態(transient analysis)電流模型推導 15 2.2.1 Gummel-Poon 模型 15 2.2.2 考慮寄生電容之電流精簡模型 17 2.3 不同頻率下之電流增益 (Beta)與M-1 之rise-time 分析 19 2.4 模型驗證 22 2.5 結論 29 Chapter 3 部分解離絕緣體上矽N 型金氧半元件之turn-off 暫態分析 30 3.1 不同頻率下之電流增益 (Beta)與M-1 之fall-time 分析 31 3.2 模型驗證 33 3.3 結論 39 Chapter 4 總結與未來工作 41 參考書目 43 | |
| dc.language.iso | zh-TW | |
| dc.title | 40 奈米部份解離絕緣體上矽金氧半元件浮動基體效應之雙載子電晶體模型 | zh_TW |
| dc.title | Modeling the Parasitic Bipolar Device in the 40nm PD SOI NMOS Device Considering the Floating Body Effect | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 98-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 葉正信,陳正雄 | |
| dc.subject.keyword | 暫態分析,寄生雙載子電晶體,絕緣體上矽金氧半, | zh_TW |
| dc.subject.keyword | transient analysis,Parasitic Bipolar Device,SOI MOS, | en |
| dc.relation.page | 45 | |
| dc.rights.note | 同意授權(全球公開) | |
| dc.date.accepted | 2010-07-15 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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