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  1. NTU Theses and Dissertations Repository
  2. 工學院
  3. 工業工程學研究所
請用此 Handle URI 來引用此文件: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/85603
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dc.contributor.advisor洪一薰(I-Hsuan Ethan Hong)
dc.contributor.authorYu-Chen Leeen
dc.contributor.author李侑澄zh_TW
dc.date.accessioned2023-03-19T23:19:30Z-
dc.date.copyright2022-07-08
dc.date.issued2022
dc.date.submitted2022-06-30
dc.identifier.citationAndrew Ng, Instructor Founder, DeepLearning.AI & Co-founder, Coursera https://www.coursera.org/learn/machine-learning Borkar, S., Karnik, T., Narendra, S., Tschanz, J., Keshavarzi, A., & De, V. (2003, June). Parameter variations and impact on circuits and microarchitecture. In Proceedings of the 40th annual Design Automation Conference (pp. 338-342). Borkar, S. (2005). Designing reliable systems from unreliable components: the challenges of transistor variability and degradation. Ieee Micro, 25(6), 10-16. Cazorla, F. J., Ramirez, A., Valero, M., & Fernández, E. (2004, December). Dynamically controlled resource allocation in SMT processors. In 37th International Symposium on Microarchitecture (MICRO-37'04) (pp. 171-182). IEEE. Chang, K. W., Huang, C. Y., Mu, S. P., Huang, J. M., Chen, S. H., & Chao, M. C. T. (2018, August). DVFS binning using machine-learning techniques. In 2018 IEEE International Test Conference in Asia (ITC-Asia) (pp. 31-36). IEEE. Chen, T., & Guestrin, C. (2016, August). Xgboost: A scalable tree boosting system. In Proceedings of the 22nd acm sigkdd international conference on knowledge discovery and data mining (pp. 785-794). Choi, S., & Yeung, D. (2006, June). Learning-based SMT processor resource distribution via hill-climbing. In 33rd International Symposium on Computer Architecture (ISCA'06) (pp. 239-251). IEEE. Humeau, S., Wijaya, T. K., Vasirani, M., & Aberer, K. (2013, October). Electricity load forecasting for residential customers: Exploiting aggregation and correlation between households. In 2013 Sustainable internet and ICT for sustainability (SustainIT) (pp. 1-6). IEEE. Inal, G., & Küçük, G. (2018, November). Application of machine learning techniques on prediction of future processor performance. In 2018 Sixth International Symposium on Computing and Networking Workshops (CANDARW) (pp. 190-195). IEEE. Intel® Core™ 處理器產品。 https://www.intel.com.tw/content/www/tw/zh/products/details/processors/core.html Ipek, E., Supinski, B. R. D., Schulz, M., & McKee, S. A. (2005, August). An approach to performance prediction for parallel applications. In European Conference on Parallel Processing (pp. 196-205). Springer, Berlin, Heidelberg. Iyer, S. G., & Pawar, A. D. (2019, November). Machine learning model for predicting price of processors using multivariate linear regression. In 2019 International Conference on Smart Systems and Inventive Technology (ICSSIT) (pp. 52-56). IEEE. Jiménez, D. A., & Lin, C. (2001, January). Dynamic branch prediction with perceptrons. In Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture (pp. 197-206). IEEE. Joseph, P. J., Vaswani, K., & Thazhuthaveetil, M. J. (2006, February). Construction and use of linear regression models for processor performance analysis. In The Twelfth International Symposium on High-Performance Computer Architecture, 2006. (pp. 99-108). IEEE. Karkhanis, T. S., & Smith, J. E. (2004, June). A first-order superscalar processor model. In Proceedings. 31st Annual International Symposium on Computer Architecture, 2004. (pp. 338-349). IEEE. List of Intel processors. https://en.wikipedia.org/wiki/List_of_Intel_processors Lo, J. L., Parekh, S. S., Eggers, S. J., Levy, H. M., & Tullsen, D. M. (1999). Software-directed register deallocation for simultaneous multithreaded processors. IEEE Transactions on Parallel and Distributed Systems, 10(9), 922-933. Machine Learning week 1: Cost Function, Gradient Descent and Univariate Linear Regression https://medium.com/@lachlanmiller_52885/machinelearning-week-1-cost-function-gradient-descent-andunivariate-linear-regression-8f5fe69815fd Maxwell, P., Hartanto, I., & Bentz, L. (2000, October). Comparing functional and structural tests. In Proceedings International Test Conference 2000 (IEEE Cat. No. 00CH37159) (pp. 400-407). IEEE. Monreal, T., González, A., Valero, M., González, J., & Viñals, V. (2000). Dynamic register renaming through virtual-physical registers. Journal of Instruction Level Parallelism, 2, 4-16. Phan, T. D. (2018, December). Housing price prediction using machine learning algorithms: The case of Melbourne city, Australia. In 2018 International Conference on Machine Learning and Data Engineering (iCMLDE) (pp. 35-42). IEEE. Sadi, M., Tehranipoor, M., Wang, X., & Winemberg, L. (2015, May). Speed binning using machine learning and on-chip slack sensors. In Proceedings of the 25th edition on Great Lakes Symposium on VLSI (pp. 155-160). Sarangi, S. R., Greskamp, B., Teodorescu, R., Nakano, J., Tiwari, A., & Torrellas, J. (2008). VARIUS: A model of process variation and resulting timing errors for microarchitects. IEEE Transactions on Semiconductor Manufacturing, 21(1), 3-13. Sharkey, J., Ponomarev, D., & Kanad Ghose, M. S. I. M. (2005). A Flexible Multithreaded Architectural Simulation Environment. CS-TR 05-DP01, State Univeristy of New York at Binghamton. Shi, Q., Wang, X., Winemberg, L., & Tehranipoor, M. M. (2016). On-chip sensor selection for effective speed-binning. Analog Integrated Circuits and Signal Processing, 88(2), 369-382. Su, M. Y., Lin, W. C., Kuo, Y. T., Li, C. M., Fang, E. J. W., & Hsueh, S. S. Y. (2021, April). Chip Performance Prediction Using Machine Learning Techniques. In 2021 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) (pp. 1-4). IEEE. The Secret Of CPU HYPERTHREADING In Depth The Secret Of CPU HYPERTHREADING In Depth (ourtechroom.com) Varma, A., Sarma, A., Doshi, S., & Nair, R. (2018, April). House price prediction using machine learning and neural networks. In 2018 second international conference on inventive communication and computational technologies (ICICCT) (pp. 1936-1939). IEEE. Viktorovich, P. A., Aleksandrovich, P. V., Leopoldovich, K. I., & Vasilevna, P. I. (2018, August). Predicting Sales Prices of the Houses Using Regression Methods of Machine Learning. In 2018 3rd Russian-Pacific Conference on Computer Technology and Applications (RPC) (pp. 1-5). IEEE. Wang, H., Koren, I., & Krishna, C. M. (2008, October). An adaptive resource partitioning algorithm for SMT processors. In Proceedings of the 17th international conference on Parallel architectures and compilation techniques (pp. 230-239). Wang, X., Tehranipoor, M., & Datta, R. (2008, November). Path-RO: A novel on-chip critical path delay measurement under process variations. In 2008 IEEE/ACM International Conference on Computer-Aided Design (pp. 640-646). IEEE. What is Machine Learning? https://deepai.org/machine-learning-glossary-and-terms/machine-learning 李侑澄. (2014). 運用層級分析法探討 [遊戲玩家 PC 硬體購買決策之關鍵因素].
dc.identifier.urihttp://tdr.lib.ntu.edu.tw/jspui/handle/123456789/85603-
dc.description.abstract本研究以桌上型主機板之處理器為主要探討標的,以研發人員的產業領域知識(Domain Knowledge)來找到影響處理器效能的關鍵參數,進行實驗室大量測試數據(Data)的整理,運用簡單的線性迴歸(Linear Regression)方法,讓主機板讀取到使用的處理器及散熱器特性後,來預測處理器在搭配的散熱器下最佳操作頻率及需求電壓,使主機板的處理器在作業系統中能以優化後的效能穩定運作,提供效能需求及內容創作的使用者能增加其使用的應用程式效能、提升使用者的工作效率。此為本研究探討的議題,除了提供效能需求的使用者更佳的體驗,也為產業數據趨動、線性迴歸的應用和發揮提供一個學術上的案例參考。zh_TW
dc.description.abstractThis research investigates the performance prediction model of desktop processors and identifies the key performance indicators affecting desktop processors performance. We apply the linear regression to the prediction of desktop processor performance so that a motherboard is able to know the capability of desktop processors and coolers. The proposed method allows us to predict the optimized operating frequency and required voltage while the operating system achieves the optimal performance at the stable status of a motherboard. The results help content creation and performance-hungry users to have a better experience over daily applications and to increase their working efficiency.en
dc.description.provenanceMade available in DSpace on 2023-03-19T23:19:30Z (GMT). No. of bitstreams: 1
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Previous issue date: 2022
en
dc.description.tableofcontents論文口試委員審定書 i 致謝 ii 摘要 iii Abstract iv 目錄 v 圖目錄 vii 表目錄 viii 第一章 緒論 1 第二章 處理器效能優化影響參數 5 2.1 處理器頻率 5 2.2 處理器核心電壓 7 2.3 處理器散熱 9 第三章 線性迴歸模型建構與流程 11 3.1 線性迴歸演算法 11 3.2 線性迴歸模型與分析流程 15 3.2.1 問題描述及目標 15 3.2.2 最佳操作頻率預測求解模型 17 3.2.3 最佳核心電壓預測求解模型 18 3.2.4 線性迴歸方法分析流程 20 第四章 預測結果分析與驗證 21 4.1 迴歸預測結果分析 21 4.1.1 預測最佳操作頻率迴歸結果 21 4.1.2 預測最佳核心電壓迴歸結果 23 4.1.3 特徵值關係圖表解析 26 4.2 穩定性驗證預測結果 30 4.2.1 穩定性測試及結果 30 4.2.2 研究總結與模型限制 33 4.2.3 線性迴歸方法結果比較 34 第五章 結論與建議 35 參考文獻 36
dc.language.isozh-TW
dc.subject處理器效能zh_TW
dc.subject效能優化zh_TW
dc.subject線性迴歸zh_TW
dc.subject線性迴歸zh_TW
dc.subject效能優化zh_TW
dc.subject處理器效能zh_TW
dc.subjectlinear regressionen
dc.subjectlinear regressionen
dc.subjectprocessor performanceen
dc.subjectperformance optimizationen
dc.subjectprocessor performanceen
dc.subjectperformance optimizationen
dc.title運用線性迴歸預測處理器效能zh_TW
dc.titlePerformance Prediction of Desktop Processors Using Linear Regressionen
dc.typeThesis
dc.date.schoolyear110-2
dc.description.degree碩士
dc.contributor.oralexamcommittee吳政鴻(Cheng-Hung Wu),黃奎隆(Kwei-Long Huang),陳文智(Wen-Chih Chen)
dc.subject.keyword線性迴歸,處理器效能,效能優化,zh_TW
dc.subject.keywordlinear regression,processor performance,performance optimization,en
dc.relation.page39
dc.identifier.doi10.6342/NTU202201148
dc.rights.note同意授權(全球公開)
dc.date.accepted2022-07-03
dc.contributor.author-college工學院zh_TW
dc.contributor.author-dept工業工程學研究所zh_TW
dc.date.embargo-lift2022-07-08-
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