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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 郭斯彥(Sy-Yen Kuo) | |
| dc.contributor.author | CHUN-CHIEH SU | en |
| dc.contributor.author | 蘇莙傑 | zh_TW |
| dc.date.accessioned | 2023-03-19T22:54:56Z | - |
| dc.date.copyright | 2022-08-12 | |
| dc.date.issued | 2022 | |
| dc.date.submitted | 2022-07-28 | |
| dc.identifier.citation | K. Gallagher, C. Caner, and J. Deignan, “The law and reverse engineering,” in 2012 19th Working Conference on Reverse Engineering, 2012, pp. 3–4 W. Choi, S. Lee, K. Joo, H. J. Jo, and D. H. Lee, “An enhanced method for reverse engineering can data payload,” IEEE Transactions on Vehicular Technology, vol. 70, no. 4, pp. 3371–33 M. Fyrbiak, S. Wallat, P. Swierczynski, M. Hoffmann, S. Hoppach, M. Wilhelm, T. Weidlich, R. Tessier, and C. Paar, “Hal—the missing piece of the puzzle for hardware reverse engineering, trojan detection and insertion,” IEEE Transactions on Dependable and Secure Computing, vol. 16, G. Fleck, W. Kirchmayr, M. Moser, L. Nocke, J. Pichler, R. Tober, and M. Wit latschil, “Experience report on building astm based tools for multilanguage reverse engineering,” in 2016 IEEE 23rd International Conference on Software Analysis, Evolution, and Reengineering (SANER), vo A. M. Villegas, “Function identification and recovery signature tool,” in 2016 11th International Conference on Malicious and Unwanted Software (MALWARE), 2016, pp. 1–3 S. Agarwal and A. Aggarwal, “Model driven reverse engineering of user interface —a comparative study of static and dynamic model generation tools,” in 2014 International Conference on Parallel, Distributed and Grid Computing, 2014, pp.268–2 A. Roozbeh, J. Soares, G. Q. Maguire, F. Wuhib, C. Padala, M. Mahloo, D. Turull, V. Yadhav, and D. Kostić, “Softwaredefined “hardware'infrastructures: A survey on enabling technologies and open research directions,” IEEE Communications Surveys Tutorials, vol. 20, no. 3, pp 2454-2485,2018 M. Chen, H. Wei, and H. Li, “Architecture design and hardware implementation of aes encryption algorithm,” in 2020 5th International Conference on Mechanical, Control and Computer Engineering (ICMCCE), 2020, pp. 1611-1614 S. K. R, S. R, M. A. M, P. K. M. S, and R. M, “Design of high speed aes system for efficient data encryption and decryption system using fpga,” in 2018 International Conference on Electrical, Electronics, Communication, Computer, and Optimization Techniques (ICEECCOT), 2018, pp, 1279-12812 P. M. Szecówka and P. W. Marucha, “Dvbcsa encryption in digital hardware,”in Proceedings of the 18th International Conference Mixed Design of Integrated Circuits and Systems MIXDES 2011, 2011, pp. 309–313. A. Nadjia and A. Mohamed, “Aes ip for hybrid cryptosystem rsaaes,” in 2015 IEEE 12th International MultiConference on Systems, Signals Devices (SSD15), 2015, pp. 1–6. B. QingHai, Z. WenBo, J. Peng, and L. Xu, “Research on design principles of elliptic curve public key cryptography and its implementation,” in 2012 International Conference on Computer Science and Service System, 2012, pp 1224-1227 W. Tao and W. Yiquan, “A binary file virtualization protection method, device, medium and electronic devi N. K. Boran, S. Rathore, M. Udeshi, and V. Singh, “Finegrained scheduling in heterogeneousisa architectures,” IEEE Computer Architecture Letters, vol. 20, no. 1, pp. 9–12, 2021. T. Jia, Y. Ju, R. Joseph, and J. Gu, “Ncpu: An embedded neural cpu architecture on resourceconstrained low power devices for realtime endtoend performance,” in 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2020, pp. 1097–1109 T. Riordan, G. Grewal, S. Hsu, J. Kinsel, J. Libby, R. March, M. Mills, P. Ries, and R. Scofield, “The mips m2000 system,” in Proceedings 1988 IEEE International Conference on Computer Design: VLSI, 1988, pp. 366–369 S. Mirapuri, M. Woodacre, and N. Vasseghi, “The mips r4000 processor,” IEEE Micro, vol. 12, no. 2, pp. 10–22, 1992. T. Riordan, G. Grewal, S. Hsu, J. Kinsel, J. Libby, R. March, M. Mills, P. Ries, and R. Scofield, “System design using the mips r3000/3010 risc chipset,” in Digest of Papers. COMPCON Spring 89. ThirtyFourth IEEE Computer Society International Conference: Intellectual Leverage, 1989, pp. 494–498. C.C. Chen, http://ccckmit.wikidot.com/ocs:cpu0, 2009,Oct,16, p. 24. L. Wang, J. Ruan, and D. Zhang, “Mips cpu test system for practice teaching,” in 2017 12th International Conference on Computer Science and Education (ICCSE), 2017, pp. 663–666. C. Lattner and V. Adve, “LLVM: A Compilation Frame work for Lifelong Program Analysis & Transformation,” in Proceedings of the 2004 International Symposium on Code Generation and Optimization (CGO’04), Palo Alto, California, Mar 2004. K. Shigenobu, K. Ootsu, T. Ohkawa, and T. Yokota, “A translation method of arm machine code to llvmir for binary code parallelization and optimization,” in 2017 Fifth International Symposium on Computing and Networking (CANDAR), 2017, pp. 575–579. K. Jingu, K. Shigenobu, K. Ootsu, T. Ohkawa, and T. Yokota, “Directivebased par allelization of forloops at llvm ir level,” in 2019 20th IEEE/ACIS International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing (SNPD), 2019, pp. 421–426. X. Tian, H. Saito, E. Su, A. Gaba, M. Masten, E. Garcia, and A. Zaks, “Llvm frame work and ir extensions for parallelization, simd vectorization and offloading,” in 2016 Third Workshop on the LLVM Compiler Infrastructure in HPC (LLVMHPC), 2016, pp. 21–31. D. Khaldi, Y. Luo, B. Yu, A. Sotkin, B. Morais, and M. Girkar, “Extending llvm ir for dpc++ matrix support: A case study with intel<sup>®</sup> advanced matrix extensions (intel<sup>®</sup> amx),” in 2021 IEEE/ACM 7th Workshop on the LLVM Compiler Infrastructure in HPC (LLVMHPC), 2021, pp. 20-26. “Iee colloquium on ’field programmable gate arrays technology and applications’ (digest no.1993/037),” in IEE Colloquium on Field Programmable Gate Arrays Technology and Applications, 1993, pp. 0 F. Hatori, T. Sakurai, K. Nogami, K. Sawada, M. Takahashi, M. Ichida, M. Uchida, I. Yoshii, Y. Kawahara, T. Hibi, Y. Saeki, H. Muroga, A. Tanaka, and K. Kanzaki, “Intro ducing redundancy in field programmable gate arrays,” in Proceedings of IEEE Custom Integrated Circuits Conference CICC ’93, 1993, pp. 7.1.1–7.1.4. H. Rajan, Appendix: ANTLR: A Brief Review, 2022, pp. 265–268 | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/85281 | - |
| dc.description.abstract | 隨著資訊科技的快速發展，大家開始注重資訊安全的問題。單純使用傳統的軟體加密技術或是硬體加密技術越來越難保證資訊安全的可靠性，尤其是現在逆向工程的技術越來越發達，很多可執行檔的 binary code 可以很輕易透過反組譯工具逆向反組譯回組合語言甚至高階語言導致一些敏感機密資料外洩。在此背景下，本論文實現了一種針對 CPU 指令集架構進行軟體與硬體整合的雙向亂序加密框架。內容包括 MIPS ISA 和 CPU0 ISA 以及其對應的高階語言 Compiler tool chain的框架設計，利用 Quartus II 17.1 做 comprehensive wiring 以及利用 Modelsim 模擬驗證，最後燒錄到 FPGA(Altera DE2115) 上，實驗結果顯示使用我們提出的框架生成出的 CPU 以及 compiler tool chain 可以正確無誤的執行並且只有微乎其微的overhead。 | zh_TW |
| dc.description.abstract | With the rapid development of information technology, everyone has begun to pay attention to the issue of information security. It is becoming more and more difficult to ensure the reliability of information security by simply using traditional software encryption technology or hardware encryption technology, especially now that the technology of reverse engineering is more and more developed, and the binary code of many executable files can be easily decompiled through reverse translation. The tool reverses and decompiles back to the combined language and even the highlevel language, which leads to the leakage of some sensitive and confidential information. Under this background, this paper implements a bidirectional outoforder encryption framework that integrates software and hardware for CPU instruction set architecture. The content includes the framework design of MIPS ISA and CPU0 ISA and their corresponding highlevel language Compiler tool chain, using Quartus II 17.1 for comprehensive wiring and M delsim simulation verification, and finally burning to FPGA (Altera DE2115), the experimental results show that using The CPU and compiler tool chain generated by our proposed framework can be executed correctly and with only minimal overhead. | en |
| dc.description.provenance | Made available in DSpace on 2023-03-19T22:54:56Z (GMT). No. of bitstreams: 1 U0001-2807202215072600.pdf: 2184626 bytes, checksum: 2bca409137a861818ca525f9b1200607 (MD5) Previous issue date: 2022 | en |
| dc.description.tableofcontents | 誌謝 i 摘要 ii Abstract iii Contents iv List of Figures vi Chapter 1 Introduction 1 Chapter 2 Related Works 5 2.1 Instruction Set Architecture . . . . . . . . . . . . . . . . . . . . . . 5 2.2 LLVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Chapter 3 Proposed Method 16 3.1 Overview of the Proposed Architecture . . . . . . . . . . . . . . . . 16 3.2 Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3 LLVM TableGen automatic generated . . . . . . . . . . . . . . . . . 19 3.4 Tool chain automatic generated . . . . . . . . . . . . . . . . . . . . 21 3.5 Hardware Verilog automatic generated . . . . . . . . . . . . . . . . . 22 3.6 Reconfigurable CPU ISA . . . . . . . . . . . . . . . . . . . . . . . . 24 Chapter 4 Experimental Results 25 4.1 Environment configuration . . . . . . . . . . . . . . . . . . . . . . . 25 4.2 ANTLR automatic generated verilog . . . . . . . . . . . . . . . . . . 27 4.3 Sorting Algorithm Function Verification . . . . . . . . . . . . . . . . 30 4.4 Hardware resource Timing . . . . . . . . . . . . . . . . . . . . . . . 30 Chapter 5 Cluclusion and Future Works 33 References 35 | |
| dc.language.iso | en | |
| dc.subject | LLVM | zh_TW |
| dc.subject | 指令集架構 | zh_TW |
| dc.subject | 中央處理器 | zh_TW |
| dc.subject | 編譯器 | zh_TW |
| dc.subject | 組合語言 | zh_TW |
| dc.subject | FPGA | zh_TW |
| dc.subject | ISA | en |
| dc.subject | assembly language | en |
| dc.subject | compiler | en |
| dc.subject | LLVM | en |
| dc.subject | FPGA | en |
| dc.subject | CPU | en |
| dc.title | 基於現場可程式化邏輯閘陣列實現可重構指令集架構 之軟硬體整合 | zh_TW |
| dc.title | Software and Hardware Integration for Reconfigurable Instruction Set Architecture based on FPGA | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 110-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 顏嗣鈞(Hsu-chun Yen),雷欽隆 (Chin-Laung Lei),陳英一(Ing-Yi Chen),游家牧(Chia-Mu Yu) | |
| dc.subject.keyword | 中央處理器,指令集架構,FPGA,LLVM,編譯器,組合語言, | zh_TW |
| dc.subject.keyword | CPU,ISA,FPGA,LLVM,compiler,assembly language, | en |
| dc.relation.page | 39 | |
| dc.identifier.doi | 10.6342/NTU202201834 | |
| dc.rights.note | 同意授權(限校園內公開) | |
| dc.date.accepted | 2022-07-29 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
| dc.date.embargo-lift | 2022-08-12 | - |
| 顯示於系所單位： | 電機工程學系 | |
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