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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/85187完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 劉深淵(Shen-Iuan Liu) | |
| dc.contributor.author | Ming-Xuan Zhan | en |
| dc.contributor.author | 詹銘軒 | zh_TW |
| dc.date.accessioned | 2023-03-19T22:49:00Z | - |
| dc.date.copyright | 2022-08-10 | |
| dc.date.issued | 2022 | |
| dc.date.submitted | 2022-08-04 | |
| dc.identifier.citation | S. Shahramian, B. Dehlaghi, and A. Chan Carusone, “Edge-based adaptation for a 1 IIR +1 discrete-time tap DFE converging in 5 µs,” IEEE J. Solid-State Circuits, vol. 51, no. 12, pp. 3192–3203, Dec. 2016. H.-J. Chi et al., “A single-loop SS-LMS algorithm with single-ended integrating DFE receiver for multi-drop DRAM interface,” IEEE J. Solid-State Circuits, vol. 46, no. 9, pp. 2053–2063, Sep. 2011. J. Lee, K. Lee, H. Kim, B. Kim, K. park, and D. Jeong, “A 0.1-pJ/b/dB 1.62-to-10.8-Gb/s video interface receiver with jointly adaptive CTLE and DFE using biased data-level reference,” IEEE J. Solid-State Circuits, vol. 55, no. 8, pp. 2186-2195, Aug.2020. J. Cao et al., “OC-192 transmitter and receiver in standard 0.18-μm CMOS,” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1768–1780, Dec. 2002. J. Lee, “A 20-Gb/s adaptive equalizer in 0.13µm CMOS technology,” IEEE J. Solid-State Circuits, vol. 41, no. 9, pp. 2058–2066, Sep. 2006. Y. M. Ying and S. I. Liu, “A 20Gb/s digitally adaptive equalizer/ DFE with blind sampling”, in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 444–445, Feb. 2011. Z. Hong, Y. Liu, and W. Chen, “A 3.12 pJ/bit, 19-27 Gbps receiver with 2-tap DFE embedded clock and data recovery,” IEEE J. Solid-State Circuits, vol. 50, no. 11, pp. 2625–2634, Nov. 2015. W. M. Chen, Y. S. Yao and S. I. Liu, 'A 20-Gb/s Jitter-Tolerance-Enhanced Digital CDR with One-Tap DFE,' IEEE Trans. Circuits and Syst. II, Exp. Briefs, vol. 69, no. 3, pp. 894-898, March 2022. J. W. Jung and B. Razavi, “A 25 Gb/s 5.8 mW CMOS equalizer,” IEEE J. Solid-State Circuits, vol. 50, no. 2, pp. 515–526, Feb. 2015. A. A. Hafez and C.-K.-K. Yang, “Analysis and design of superharmonic injection-locked multipath ring oscillators,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 60, no. 7, pp. 1712–1725, Jul. 2013. I. Ozkaya et al., “A 60-Gb/s 1.9-pJ/bit NRZ optical receiver with low-latency digital CDR in 14-nm CMOS FinFET,” IEEE J. Solid-State Circuits, vol. 53, no. 4, pp. 1227–1237, Apr. 2018. H. Won et al., “A 28-Gb/s receiver with self-contained adaptive equalization and sampling point control using stochastic sigma-tracking eye-opening monitor,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 64, no. 3, pp. 664–674, Mar. 2017. Y.-H. Kim, Y.-J. Kim, T. Lee, and L.-S. Kim, “A 21-Gbit/s 1.63-pJ/bit adaptive CTLE and one-tap DFE with single loop spectrum balancing method,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 24, no. 2, pp. 789–793, Feb. 2016. S. Ibrahim and B. Razavi, “Low-power CMOS equalizer design for 20-Gb/s systems,” IEEE J. Solid-State Circuits, vol. 46, no. 6, pp. 1321–1336, June 2011. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/85187 | - |
| dc.description.abstract | 本論文實現一個資料傳輸速率為一百六十億位元每秒的線性等化器與具適應時間0.3微秒的決策回授等化器。藉由使用斜率偵測器切換符號-符號最小均方演算法的步長來達到快速收斂。以資料序列為PRBS7下的量測，通道衰減為-10.3dB到-24.3dB，資料錯誤率<10^-12。量測到的收斂時間小於0.3微秒。此等化器使用台積電40奈米製程製作，核心電路面積為0.179mm^2。最後，等化器的功率消耗為38毫瓦，達到的能量效率為0.098pJ/bit/dB。 | zh_TW |
| dc.description.abstract | In this thesis, a 16-Gb/s linear equalizer and decision-feedback equalizer (DFE) using the proposed sign-sign least-mean-square (SSLMS) is presented. Using the slope detector to switch the step size of the SSLMS to achieve fast convergence. Measured with PRBS of 2^7–1, the bit error rates are all less than 10^-12 for channel loss from –10.3 to –24.3dB. The measured convergence time of the proposed SSLMS are determined within 0.3us. This equalizer circuit is fabricated in 40-nm CMOS technology and occupies an active area of 0.179 mm^2. Finally, the power consumption of the equalizers is 38mW, and the calculated energy efficiency is 0.098pJ/bit/dB. | en |
| dc.description.provenance | Made available in DSpace on 2023-03-19T22:49:00Z (GMT). No. of bitstreams: 1 U0001-0408202214313800.pdf: 3705084 bytes, checksum: 22ecc95e4827a4d5bd3cb8897d28f0ca (MD5) Previous issue date: 2022 | en |
| dc.description.tableofcontents | 1. 引言................................................................1 1.1 概論...............................................................1 1.2 有線通訊系統........................................................1 1.3 等化器.............................................................3 1.3.1 前饋式等化器......................................................3 1.3.2 連續時間線性等化器................................................3 1.3.3 決策回授等化器....................................................4 1.4 論文組織...........................................................5 2.一個一百六十億位元每秒的線性等化器與具適應時間0.3微秒的決策回授等化器.....6 2.1 研究動機...........................................................6 2.2 提出的SSLMS原理....................................................7 2.2.1 提出的SSLMS演算法................................................7 2.2.2 斜率偵測器.......................................................9 2.3 電路描述...........................................................13 2.3.1 連續時間線性等化器................................................15 2.3.2 決策回授等化器....................................................18 2.3.3 其他電路.........................................................20 2.4 量測結果...........................................................24 3. 結論及未來改善.......................................................34 3.1 結論...............................................................34 3.2 未來改善...........................................................35 參考文獻...............................................................36 | |
| dc.language.iso | zh-TW | |
| dc.subject | 決策回授等化器 | zh_TW |
| dc.subject | 符號-符號最小均方演算法 | zh_TW |
| dc.subject | 連續時間線性等化器 | zh_TW |
| dc.subject | Sign-Sign Least-Mean-Square | en |
| dc.subject | Continuous-Time Linear Equalizer | en |
| dc.subject | Decision-Feedback Equalizer | en |
| dc.title | 一個一百六十億位元每秒的線性等化器與具自適應時間0.3微秒的決策回授等化器 | zh_TW |
| dc.title | A 16-Gb/s Linear Equalizer and Decision-Feedback Equalizer With an Adaptation Time of 0.3us | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 110-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 林宗賢(Tsung-Hsien Lin),李泰成(Tai-Cheng Lee),楊清淵(Ching-Yuan Yang),鄭國興(Kuo-Hsing Cheng) | |
| dc.subject.keyword | 連續時間線性等化器,決策回授等化器,符號-符號最小均方演算法, | zh_TW |
| dc.subject.keyword | Continuous-Time Linear Equalizer,Decision-Feedback Equalizer,Sign-Sign Least-Mean-Square, | en |
| dc.relation.page | 37 | |
| dc.identifier.doi | 10.6342/NTU202202058 | |
| dc.rights.note | 同意授權(限校園內公開) | |
| dc.date.accepted | 2022-08-05 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| dc.date.embargo-lift | 2022-08-10 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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