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  1. NTU Theses and Dissertations Repository
  2. 電機資訊學院
  3. 電子工程學研究所
Please use this identifier to cite or link to this item: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/85139
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dc.contributor.advisor林宗賢(Tsung-Hsien Lin)
dc.contributor.authorHao Yanen
dc.contributor.author顏浩zh_TW
dc.date.accessioned2023-03-19T22:46:03Z-
dc.date.copyright2022-08-12
dc.date.issued2022
dc.date.submitted2022-08-10
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Lacaita, 'Multipath Adaptive Cancellation of Divider Non-Linearity in Fractional-N PLLs,' 2011 IEEE International Symposium of Circuits and Systems (ISCAS), pp. 418-421, May 2011. [14] R. B. Staszewski et al., 'Spur-Free All-Digital PLL in 65nm for Mobile Phones,' 2011 IEEE International Solid-State Circuits Conference, pp. 52-54, Feb. 2011. [15] M. SafiHarb and G. W. Roberts, “70-GHz Effective Sampling Time Base On-Chip Oscilloscope in CMOS,” IEEE J. Solid-State Circuits, vol. 42, no. 8, pp. 1743–1757, Aug. 2007. [16] J. Z. Ru, C. Palattella, P. Geraedts, E. Klumperink and B. Nauta, 'A High-Linearity Digital-to-Time Converter Technique: Constant-Slope Charging,' IEEE Journal of Solid-State Circuits, vol. 50, no. 6, pp. 1412-1423, Jun. 2015. [17] P. Chen, F. Zhang, Z. Zong, S. Hu, T. Siriburanon and R. B. Staszewski, 'A 31-mW, 148-fs Step, 9-bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28-nm CMOS,' IEEE Journal of Solid-State Circuits, vol. 54, no. 11, pp. 3075-3085, Nov. 2019. [18] B. Razavi, 'The Strong-Arm Latch [A Circuit for All Seasons],' IEEE Solid-State Circuits Magazine, vol. 7, no. 2, pp. 12-17, Spr. 2015. [19] Y. Donnelly and M. P. Kennedy, 'Prediction of Phase Noise and Spurs in a Nonlinear Fractional-N Frequency Synthesizer,' IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 11, pp. 4108-4121, Nov. 2019. [20] P. Chen, X. Huang and R. B. Staszewski, 'Fractional Spur Suppression in All-Digital Phase-Locked Loops,' IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2565-2568, Jul. 2015. [21] J. Lee and H. Wang, 'Study of Subharmonically Injection-Locked PLLs,' IEEE Journal of Solid-State Circuits, vol. 44, no. 5, pp. 1539-1553, May 2009. [22] Y. H. Tseng, C. W. Yeh and S. I. Liu, 'A 2.25–2.7 GHz Area-Efficient Subharmonically Injection-Locked Fractional-N Frequency Synthesizer with a Fast-Converging Correlation Loop,' IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 4, pp. 811-822, Apr. 2017. [23] J. Gong et al., “1.33 mW, 1.6 psrms -Integrated-Jitter, 1.8–2.7 GHz Ring-Oscillator-Based Fractional-N Injection-Locked DPLL for Internet-of-Things applications,” Proc. IEEE Radio Freq. Integr. Circuits Symp. (RFIC), Philadelphia, PA, USA, pp. 44–47, Jun. 2018. [24] A. Santiccioli, M. Mercandelli, A. L. Lacaita, C. Samori and S. Levantino, 'A 1.6-to-3.0-GHz Fractional-N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power,' IEEE Journal of Solid-State Circuits, vol. 54, no. 11, pp. 3149-3160, Nov. 2019. [25] Q. Zhang, S. Su, C. R. Ho and M. S. W. Chen, 'A Fractional-N Digital MDLL With Background Two-Point DTC Calibration,' IEEE Journal of Solid-State Circuits, vol. 57, no. 1, pp. 80-89, Jan. 2022. [26] X. Gao, E. A. M. Klumperink, P. F. J. Geraedts, and B. Nauta, “Jitter Analysis and a Benchmarking Figure-of-Merit for Phase-Locked loops,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 56, no. 2, pp. 117–121, Feb. 2009. [27] H. Zhang et al., '0.2mW 70Fsrms-Jitter Injection-Locked PLL Using De-Sensitized SSPD-Based Injecting-Time Self-Alignment Achieving -270dB FoM and -66dBc Reference Spur,' 2019 Symposium on VLSI Circuits, pp. C38-C39.5-248, Apr. 2019. [28] K. L. Chan, N. Rakuljic and I. Galton, 'Segmented Dynamic Element Matching for High-Resolution Digital-to-Analog Conversion,' IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 55, no. 11, pp. 3383-3392, Dec. 2008.
dc.identifier.urihttp://tdr.lib.ntu.edu.tw/jspui/handle/123456789/85139-
dc.description.abstract本論文呈獻一個輸入參考時脈信號頻率為60百萬赫茲,操作於24億赫茲,具有數位延遲轉換器延遲範圍縮小技術且以環形振盪器為基礎之小數型次取樣鎖相迴路。此架構運用環形振盪器多相位輸出對量化雜訊的粗略補償,即數位延遲轉換器延遲範圍縮小技術,從而能夠使用高精度及高線性度之數位延遲轉換器,壓制頻寬内的量化雜訊。受益於次取樣鎖相迴路和數位延遲轉換器延遲範圍縮小技術,故此架構可利用6百萬赫茲高頻寬壓制環形振盪器雜訊,以達成低的頻寬外雜訊。本論文采用多個數位校正迴路包括數位延遲轉換器增益誤差校正迴路,次取樣電荷泵和比較器輸入偏移誤差抵消迴路和環形振盪器相位誤差補償迴路,以降低實際電路非線性的影響,以至於此頻率合成器能達到極佳的表現。 這個架構在九十奈米製程所設計。其主要面積為0.07537平方毫米且在1 伏特的電源供應下總共消耗10.18毫瓦。在24億赫茲操作下,相對於主頻率1百萬赫茲處模擬到的相位雜訊為 -116.7 dBc/Hz。其均方根抖動量為479.6飛秒 (積分範圍為10千赫茲到40百萬赫茲),品質因數(figure-of-merit)為 -236.3 dB。參考突波為 -64.4 dBc且小數突波小於 -60 dBc。zh_TW
dc.description.abstractThis thesis presents a 2.4-GHz ring-VCO-based fractional-N sub-sampling phase-locked loop with a 60-MHz input reference clock and a digital-to-time converter delay range reduction technique. This architecture uses the ring-VCO multi-phase outputs to coarsely compensate the quantization noise (that is the digital-to-time converter delay range reduction technology) so that the digital-to-time converter with high precision and high linearity can be designed to suppress the quantization noise in the loop bandwidth. Benefiting from sub-sampling phase-locked loop and digital-to-time converter delay range reduction technology, the architecture can suppress ring-VCO phase noise with a high loop bandwidth of 6 MHz to achieve low out-of-loop-bandwidth noise. Multiple digital calibration loops including DTC gain error calibration loop (DTCGL), VCO phase mismatch compensation loop (PMCL), SSCP and comparator offset mismatch cancellation loop (OFMCL) are proposed to reduce the effects of real circuits nonlinearity, so that this frequency synthesizer can achieve excellent performance. This architecture is implemented in a 90nm CMOS process. The core area is 0.07537 mm2 and consumes a total of 10.18 mW with the 1-V power supply. At 2.4 GHz, the simulated phase noise at 1 MHz offset is -116.7 dBc/Hz. Its rms jitter is 479.6 fs (integrated from 10 kHz to 40 MHz) and figure-of-merit is -236.3 dB. The reference spur is -64.4 dBc and the low fractional spur is less than -60 dBc.en
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Previous issue date: 2022
en
dc.description.tableofcontentsTable of Contents 中文審定書 i 英文審定書 iii 摘要 vii Abstract ix List of Figures xiii List of Tables xvii Chapter 1 Introduction 1 1.1 Motivation and Research Goals 1 1.2 Thesis Overview 2 Chapter 2 Fundamental of High Performance Fractional-N PLL and Prior Art 5 2.1 Basics of Integer-N Charge Pump and Sub-Sampling PLL 5 2.2 Basics of Fractional-N Sub-Sampling PLL with Quantization Error Compensation Methods 7 2.2.1 DTC-Based Quantization Error Compensation Methods 8 2.2.2 Pipelined Phase-Interpolator-Based Compensation Methods 10 Chapter 3 Design of Proposed Fractional-N Ring-VCO-Based Sub-Sampling PLL with DTC Delay Range Reduction 13 3.1 Proposed Fractional-N Ring-VCO-Based Sub-Sampling PLL with DTC Delay Range Reduction 13 3.1.1 Fractional-N Control Words Block (FNCW) 15 3.1.1 DTC Gain Error Calibration Loop 16 3.1.2 VCO Phase Mismatch Compensation Loop 21 3.1.3 SSCP and Comparator Offset Mismatch Cancellation Loop 28 3.1.4 Co-Operation of Calibration Loops 31 3.2 Linear Phase-Domain Model of Proposed PLL 34 Chapter 4 Circuit Implementation 39 4.1 Digital-to-Time Converter 39 4.2 Comparator 46 4.3 Capacitor-Based Digital-to-Analog Converter 48 4.4 Timing Control Circuit 49 4.5 Ring-VCO 51 4.6 VCO Phase Selector 52 4.7 Sub-Sampling Phase Detector and Charge Pump 53 4.8 Frequency-Locked Loop 54 4.9 Area and Power Dissipation 57 Chapter 5 Simulation Results 59 5.1 Nonlinear System Simulation (AMS Simulation) 59 5.2 Phase Noise and Spurs 61 5.3 Comparison 72 Chapter 6 Conclusions and Future Works 73 6.1 Conclusions 73 6.2 Future Works 74 References 77 Appendix 81
dc.language.isoen
dc.subject小數型次取樣鎖相迴路zh_TW
dc.subject數位校正迴路zh_TW
dc.subject數位延遲轉換器延遲範圍縮小技術zh_TW
dc.subject環形振盪器多相位輸出zh_TW
dc.subjectdigital-to-time converter delay range reduction techniqueen
dc.subjectdigital calibration loopsen
dc.subjectFractional-N sub-sampling phase-locked loopen
dc.subjectring-VCO multi-phase outputsen
dc.title一個具有數位延遲轉換器延遲範圍縮小技術且以環形振盪器為基礎之小數型次取樣鎖相迴路zh_TW
dc.titleA Ring-VCO-Based Fractional-N Sub-Sampling PLL with a DTC-Range-Reduction Techniqueen
dc.typeThesis
dc.date.schoolyear110-2
dc.description.degree碩士
dc.contributor.oralexamcommittee呂良鴻(Liang-Hung Lu),蔡宗亨(Tsung-Heng Tsai)
dc.subject.keyword小數型次取樣鎖相迴路,環形振盪器多相位輸出,數位延遲轉換器延遲範圍縮小技術,數位校正迴路,zh_TW
dc.subject.keywordFractional-N sub-sampling phase-locked loop,ring-VCO multi-phase outputs,digital-to-time converter delay range reduction technique,digital calibration loops,en
dc.relation.page81
dc.identifier.doi10.6342/NTU202202241
dc.rights.note同意授權(限校園內公開)
dc.date.accepted2022-08-10
dc.contributor.author-college電機資訊學院zh_TW
dc.contributor.author-dept電子工程學研究所zh_TW
dc.date.embargo-lift2022-08-12-
Appears in Collections:電子工程學研究所

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