請用此 Handle URI 來引用此文件：
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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李致毅(Jri Lee) | |
| dc.contributor.author | Jian-Jr Su | en |
| dc.contributor.author | 蘇健智 | zh_TW |
| dc.date.accessioned | 2023-03-19T22:42:02Z | - |
| dc.date.copyright | 2022-08-18 | |
| dc.date.issued | 2022 | |
| dc.date.submitted | 2022-08-15 | |
| dc.identifier.citation | [1] A. R. Zamanov, V. A. Erokhin and P. S. Fedotov, 'ASIC-resistant hash functions,' IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus), pp. pp. 394-396, 2018. [2] 'ethminer,' [Online]. Available: https://github.com/ethereum-mining/ethminer. [3] W.-K. Chang, A high-performance memory subsystem tailored to applications with heavy bandwidth requirement. [Unpublished master's thesis] National Taiwan University. [4] Xilinx, 'VCU1525 Reconfigurable Acceleration Platform User Guide(UG1268),' 2019. [Online]. Available: https://docs.xilinx.com/v/u/en-US/ug1268-vcu1525-reconfig-accel-platform. [5] Xilinx, 'Alveo U50 Data Center Accelerator Card Data Sheet(DS965),' 2020. [Online]. Available: https://docs.xilinx.com/v/u/en-US/ds965-u50. [6] Xilinx, 'ultrascale-plus-fpga-product-selection-guide,' [Online]. Available: https://www.xilinx.com/content/dam/xilinx/support/documents/selection-guides/ultrascale-plus-fpga-product-selection-guide.pdf. [7] Xilinx, 'AXI High Bandwidth Memory Controller v1.0 (PG276),' 08 2021. [Online]. Available: https://docs.xilinx.com/r/en-US/pg276-axi-hbm/Overview. [8] G. Fowler, L. . C. Noll and P. Vo, 'FNV Hash,' [Online]. Available: http://www.isthe.com/chongo/tech/comp/fnv/#FNV-param. [9] G. Bertoni, . J. Daemen, M. Peeters and . G. . V. Assche, 'Keccak specifications,' 10 09 2009. [Online]. Available: https://keccak.team/obsolete/Keccak-specifications-2.pdf. [10]Xilinx, 'UltraScale Architecture DSP Slice User Guide(UG579),' 2021. [Online]. Available: https://docs.xilinx.com/v/u/en-US/ug579-ultrascale-dsp. [11] 'Proper SHA3 implementation,' [Online]. Available: https://github.com/phusion/digest-sha3-ruby/issues/5#issuecomment-149087749. [12] 'Which cryptographic hash function does Ethereum use?,' [Online]. Available: https://ethereum.stackexchange.com/a/554. [13] JEDEC, 'HIGH BANDWIDTH MEMORY (HBM) DRAM,' 2021. [Online]. Available: https://www.jedec.org/standards-documents/docs/jesd235a. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/85075 | - |
| dc.description.abstract | 乙太坊是現今相當熱門的區塊鏈，其發明者希望以太坊能做為世界各地人們一起驅動的世界電腦。隨著乙太坊所用的代幣價格提升，如何有效率地進行其所使用的工作量證明Ethash，其重要性也跟著日益升高。 根據Ethash的設計，電路的運算能力和其所配備大容量記憶體的頻寬成正比。最常見的高頻寬電子產品是繪圖處理器(GPU)。除此之外，也有部分現場可程式化邏輯閘陣列(FPGA)配備有高頻寬記憶體(HBM)。這類型的FPGA也因此適合計算Ethash。本篇論文描述如何在FPGA上實作硬體電路以利用HBM的頻寬，將頻寬完整轉化為Ethash的運算能力。首先透過流水線設計提高時脈。流水線設計所增加的正反器(Flip-Flop)可能導致電路無法完整放入晶片，或由於硬體資源使用率過高導致繞線困難反而降低時脈。於是進一步透過調整資料流提升硬體使用效率並精簡使用硬體資源。另外也對除法器進行改良，透過乘法器來實作。最終讓運算能力提升一倍達到81.25MH/s，同時面積縮小超過二分之一，可以將電路移植到更小的晶片上。 本篇論文並彙整過程中使用的研究方法，對於演算法資料流的分析，可以有效協助開發者找到實作架構中的瓶頸所在，期望這個方法能運用在未來其他類似開發工作中。 | zh_TW |
| dc.description.abstract | Ethereum is a popular blockchain nowadays. Its inventor has a rather ambitious vision to make it the computer which is driven by people from all over the world. In addition to blockchain-related applications, the importance of efficiently calculating Ethash, one of the proof-of-work (PoW) functions, has risen as the price of the tokens used in Ethereum has increased. According to Ethash's design, the computation capacity is proportional to the bandwidth of large-capacity memory. In addition to GPUs, there are also field programmable logic gate arrays (FPGAs) equipped with high-bandwidth memory (HBM) to handle some of the tasks with high bandwidth requirements. This paper describes a design of hardware circuits on FPGAs that is capable of fully utilizing the bandwidth of HBM and getting the most computation capacity. The first step is to improve the clock rate by pipelining. A pipeline design using too many flip-flops may cause the circuit too big to fit in the chip completely. The circuit that is too big may also reduce the timing due to high hardware resource usage. The high hardware resource usage would make electronic-design-automation (EDA) tools hard to route the circuit. Therefore, I further improve the efficiency of hardware usage and reduce the use of hardware resources by adjusting the data flow. In addition, I use a multiplier to implement the divider. Eventually, I manage to raise the computation capacity to 81.25MH/s, and the area of the circuit is reduced by more than one-half, allowing the circuit to be ported to a smaller chip. This paper also compiles the research methods used in the process. These methods of analyzing the algorithmic data flow can effectively help developers to find the bottlenecks in the implementation architecture, which can be applied to other similar development work in the future. | en |
| dc.description.provenance | Made available in DSpace on 2023-03-19T22:42:02Z (GMT). No. of bitstreams: 1 U0001-2507202221540500.pdf: 1124402 bytes, checksum: 23ae6a91db54ec53dcf1fec4cb91c03b (MD5) Previous issue date: 2022 | en |
| dc.description.tableofcontents | Contents Page Acknowledgment i 摘要 ii Abstract iii Contents iv List of Figures vi List of Tables vi Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Organization of the Thesis 2 Chapter 2 Preliminaries 3 2.1 The Property of Ethash Algorithm 3 2.2 Problem Statement 4 2.2.1 Relations between Throughput, Bandwidth, Utilization, and Hash rate 4 2.2.2 Maximize Utilization of each Circuit 5 Chapter 3 Ethash Data Flow Optimization 7 3.1 Design Methodologies on FPGA 7 3.2 Design Consideration 8 3.2.1 Clock Rate Requirement 8 3.2.2 Lower Parallel Requirement 9 3.2.3 Fully Utilize every Component 9 3.3 Component of the Design 9 3.3.1 Overview of the System 9 3.3.2 Chain Structure 10 3.4 Components in Engine 11 3.4.1 Mix-data Storage 12 3.4.2 DAG Related Part 12 3.4.3 FNV Group 12 3.5 Problems need to be solved 13 3.5.1 Fix the Timing Issue 13 3.5.2 Fixing the Latency Issue 15 3.5.3 Fixing the Utilization Issue 17 3.6 Optimization of implementation 18 3.6.1 Divider Composed with Multiplier 18 3.6.2 Read-port Prefetch Mix-data 19 3.7 Distinguish Idle Part of Circuit 19 3.7.1 Compress Idle 20 3.7.2 Keccak Hardware Sharing 22 3.7.3 Engine Combine 23 3.8 Final Design 25 3.8.1 Check Utilization 25 3.9 Monitor Module 26 3.9.1 High Ratio 26 3.9.2 High Counter 26 3.10 Result 27 3.10.1 Improvement in timing 27 3.10.2 Improvement in area 28 3.11 Technique for Optimization 28 3.11.1 Block Diagram of Data flow 29 3.11.2 Timing Issue 30 Chapter 4 Conclusion 32 4.1 Review 32 4.2 Future Work 32 Reference 34 Appendix A Keccak and SHA-3 36 A.1 Difference between Keccak and SHA-3 36 List of Figures Figure 2‑1 Computation of Ethash 3 Figure 3‑1 Design methodology 8 Figure 3‑2 Components of the system 10 Figure 3‑3 Components in Mix-function (solid line) 12 Figure 3‑4 Formulas of Keccak function [9] 13 Figure 3‑5 FNV implementation 15 Figure 3‑6 Computation of Mix-hash in Compress 20 Figure 3‑7 New design of Compress with only one FNV unit 21 Figure 3‑8 Buffer position change 22 Figure 3‑9 A circuit used to merge 2 channels into one channel 24 Figure 3‑10 Data flow example 30 Figure 3‑11 Monitor_top connection 31 List of Tables Table 3‑1 Naming of each data 11 Table 3‑2 Comparison of timing and hash rate 27 Table 3‑3 Area reduced in Engeth_top and Engine 28 Table 3‑4 Area reduced in each module of Engine 28 | |
| dc.language.iso | en | |
| dc.subject | 現場可程式化邏輯閘陣列 | zh_TW |
| dc.subject | 區塊鏈 | zh_TW |
| dc.subject | 除法器 | zh_TW |
| dc.subject | 資料流 | zh_TW |
| dc.subject | Ethash | zh_TW |
| dc.subject | Divider | en |
| dc.subject | Blockchain | en |
| dc.subject | Ethash | en |
| dc.subject | Field-Programmable Gate Array | en |
| dc.subject | Data Flow | en |
| dc.title | 以在 FPGA 實作 Ethash 探討資料流最佳化 | zh_TW |
| dc.title | Exploring Data Flow Optimization Design by Implementing Ethash on FPGAs | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 110-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 盧奕璋(Yi-Chang Lu),劉宗德(Tsung-Te Liu) | |
| dc.subject.keyword | 區塊鏈,Ethash,現場可程式化邏輯閘陣列,資料流,除法器, | zh_TW |
| dc.subject.keyword | Blockchain,Ethash,Field-Programmable Gate Array,Data Flow,Divider, | en |
| dc.relation.page | 36 | |
| dc.identifier.doi | 10.6342/NTU202201715 | |
| dc.rights.note | 同意授權(限校園內公開) | |
| dc.date.accepted | 2022-08-16 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| dc.date.embargo-lift | 2022-08-18 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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