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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳信樹(Hsin-Shu Chen) | |
dc.contributor.advisor | 陳信樹(Hsin-Shu Chen | hschen@ntu.edu.tw | ), | |
dc.contributor.author | Chen-Chun Liu | en |
dc.contributor.author | 劉正群 | zh_TW |
dc.date.accessioned | 2023-03-19T22:28:29Z | - |
dc.date.copyright | 2022-10-20 | |
dc.date.issued | 2022 | |
dc.date.submitted | 2022-09-28 | |
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Welbers, 'Matching properties of MOS transistors,' in IEEE Journal of Solid-State Circuits, vol. 24, no. 5, pp. 1433-1439, Oct. 1989 [6] Y. S. Hu et al., “A 0.6V 6.4fJ/conversion-step 10-bit 150MS/s Subranging SAR ADC in 40nm CMOS,” in IEEE Asian Solid-State Circuits Conf. Dig. Tech. Papers, pp. 81-84, Nov. 2014. [7] P.-C. Huang, et al., “An 8-bit 900MS/s Two-Step SAR ADC,” in IEEE Int. Symp. Circuits and Systems, pp. 2898-2898, May. 2016. [8] T. S. T et al. “12-b 800-MS/s TI SAR ADC with Timing Skew Calibration in 28nm CMOS”, Nov. 2019 [9] E. Swindlehurst et al., 'An 8-bit 10-GHz 21-mW TI SAR ADC With Grouped DAC Capacitors and Dual-Path Bootstrapped Switch,' in IEEE Journal of Solid-State Circuits, vol. 56, no. 8, pp. 2347-2359, Aug. 2021 [10] D. Janke, A. Monk, E. Swindlehurst, K. Layton, and S. -H. W. Chiang, 'A 9-Bit 10-MHz 28- μ W SAR ADC Using Tapered Bit Periods and a Partially Interdigitated DAC,' in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 2, pp. 187-191, Feb. 2019 [11] Y. Chung and S. Shih, 'A 10-bit 100-MS/s SAR ADC with capacitor swapping technique in 90-nm CMOS,' 2017 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2017 [12] D. -J. Chang, M. Choi, and S. -T. Ryu, 'A 28-nm 10-b 2.2-GS/s 18.2-mW Relative-Prime Time-Interleaved Sub-Ranging SAR ADC With On-Chip Background Skew Calibration,' in IEEE Journal of Solid-State Circuits, vol. 56, no. 9, pp. 2691-2700, Sept. 2021 [13] N. Kurosawa, H. Kobayashi, K. Maruyama, H. Sugawara, and K. Kobayashi, 'Explicit analysis of channel mismatch effects in time-interleaved ADC systems,' in IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 48, no. 3, pp. 261-271, March. 2001 [14] C.-C. Liu et al.,” A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation,” in IEEE ISSCC Dig. Tech. Papers, pp. 386-387, Feb. 2010 [15] P.-C. Huang, et al., “An 8-bit 900MS/s Two-Step SAR ADC,” in IEEE Int. Symp. Circuits and Systems, pp. 2898-2898, May. 2016. [16] F. Kuttner, 'A 1.2V 10b 20MSample/s non-binary successive approximation ADC in 0.13/spl mu/m CMOS,' in IEEE ISSCC Dig. Tech. Papers, pp. 176-177, Feb. 2002. [17] H.-Y. Tai, et al., “A 0.85fJ/conversion-step 10b 200kS/s Subranging SAR ADC in 40nm CMOS,” in IEEE ISSCC Dig. Tech. Papers, pp. 196-197, Feb. 2014. [18] G. Huang, S. Chang, C. Liu, and Y. Lin, 'A 1-µW 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications,' IEEE Journal of Solid-State Circuits, pp. 2783-2795, Nov. 2012. [19] X. Wang, F. Li, and Z. Wang, 'A novel autocorrelation-based timing mismatch Calibration strategy in Time-Interleaved ADCs,' 2016 IEEE International Symposium on Circuits and Systems (ISCAS). 2016 [20] M. El-Chammas and B. Murmann, 'A 12-GS/s 81-mW 5-bit Time-Interleaved Flash ADC With Background Timing Skew Calibration,' in IEEE Journal of Solid-State Circuits, vol. 46, no. 4, pp. 838-847. April 2011 [21] M. Guo, J. Mao, S. -W. Sin, H. Wei, and R. P. Martins, 'A 29mW 5GS/s Time-interleaved SAR ADC achieving 48.5dB SNDR With Fully-Digital Timing Skew Calibration Based on Digital-Mixing,' 2019 Symposium on VLSI Circuits. 2019 [22] M. Ni, X. Wang, F. Li, W. Rhee, and Z. Wang, 'A 13-Bit 2-GS/s Time-Interleaved ADC With Improved Correlation-Based Timing Skew Calibration Strategy,' in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 69, no. 2, pp. 481-494, Feb. 2022 [23] X. Wang, F. Li, W. Jia, and Z. Wang, 'A 14-Bit 500-MS/s Time-Interleaved ADC With Autocorrelation-Based Time Skew Calibration,' in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 3, pp. 322-326. March 2019 [24] H. Wei, P. Zhang, B. D. Sahoo, and B. Razavi, 'An 8 Bit 4 GS/s 120 mW CMOS ADC,' IEEE Journal of Solid-State Circuits, pp. 1751-1761. Aug. 2014. [25] S. Lee, A. P. Chandrakasan and H. Lee, 'A 1 GS/s 10b 18.9 mW TI SAR ADC With Background Timing Skew Calibration,' IEEE Journal of Solid-State Circuits, pp. 2846-2856, Dec. 2014. [26] J. Song, K. Ragab, X. Tang, and N. Sun, 'A 10-b 800-MS/s TI SAR ADC With Fast Variance-Based Timing Skew Calibration,' IEEE Journal of Solid-State Circuits, pp. 2563-2575, Oct. 2017. [27] H. -W. Kang, H. -K. Hong, S. Park, K. -J. Kim, K. -H. Ahn, and S. -T. Ryu, 'A Sign-Equality-Based Background Timing-Mismatch Calibration Algorithm for Time-Interleaved ADCs,' IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, no. 6, pp. 518-522, June. 2016 [28] H. Kang, H. Hong, W. Kim, and S. Ryu, 'A Time-Interleaved 12-b 270-MS/s SAR ADC With Virtual-Timing-Reference Timing Skew Calibration Scheme,' in IEEE Journal of Solid-State Circuits, vol. 53, no. 9, pp. 2584-2594, Sept. 2018 [29] C. Lin, Y. Wei, and T. Lee, '27.7 A 10b 2.6GS/s TI SAR ADC with background Timing Skew calibration,' in IEEE ISSCC Dig. Tech. Papers, pp. 468-469, Feb.2016. [30] N. Le Dortz et al., '22.5 A 1.62GS/s TI SAR ADC with digital background mismatch calibration achieving interleaving spurs below 70dBFS,' IEEE Journal of Solid-State Circuits, pp. 386-388, Feb. 2014. [31] D. Stepanovic and B. Nikolic, 'A 2.8 GS/s 44.6 mW Time-Interleaved ADC Achieving 50.9 dB SNDR and 3 dB Effective Resolution Bandwidth of 1.5 GHz in 65 nm CMOS,' IEEE Journal of Solid-State Circuits, pp. 971-982, April. 2013. [32] D. Li, Z. Zhu, R. Ding, M. Liu, Y. Yang, and N. Sun, 'A 10-Bit 600-MS/s TI SAR ADC With Interpolation-Based Timing Skew Calibration,' IEEE Transactions on Circuits and Systems II: Express Briefs, pp. 16-20, Jan. 2019. [33] C. Wang and J. Wu, 'A Multiphase Timing Skew Calibration Technique Using Zero-Crossing Detection,' in IEEE Transactions on Circuits and Systems I: Regular Papers, pp. 1102-1114, June. 2009. [34] Chung-Yi Wang and Jieh-Tsorng Wu, 'A background Timing Skew calibration technique for time-interleaved analog-to-digital converters,' IEEE Transactions on Circuits and Systems II: Express Briefs, pp. 299-303, April. 2006. [35] T. Miki et al., 'A 4.2 mW 50 MS/s 13-bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques,' IEEE Journal of Solid-State Circuits, pp.1372-1381, June. 2015. [36] S. A. Zahrai, N. Le Dortz, and M. Onabajo, 'Design of clock generation circuitry for high-speed Subranging time-interleaved ADCs,' IEEE International Symposium on Circuits and Systems (ISCAS), 2017. [37] B. Wicht, T. Nirschl and D. Schmitt-Landsiedel, 'Yield and speed optimization of a latch-type voltage sense amplifier,' IEEE Journal of Solid-State Circuits, pp. 1148-1158, July. 2004. [38] M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. A. M. Klumperink and B. Nauta, 'A 10-bit Charge-Redistribution ADC Consuming 1.9uW at 1 MS/s,' IEEE Journal of Solid-State Circuit, pp. 1007-1015, May. 2010. [39] C. Liu, S. Chang, G. Huang, and Y. Lin, 'A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure,' IEEE Journal of Solid-State Circuits, pp. 731-740, April. 2010 [40] Shuo-Wei Mike Chen and R. W. Brodersen, 'A 6b 600MS/s 5.3mW Asynchronous ADC in 0.13/spl mu/m CMOS,' in IEEE ISSCC Dig. Tech. Papers, pp. 2350-2359, Feb. 2006. [41] J. Mulder et al., 'An 800MS/s dual-residue pipeline ADC in 40nm CMOS,' in IEEE ISSCC Dig. Tech. Papers, pp. 184-18, Feb. 2011. [42] Yuan-Ching Lien, 'A 14.6mW 12b 800MS/s 4×time-interleaved pipelined SAR ADC achieving 60.8dB SNDR with Nyquist input and sampling timing skew of 60fsrms without calibration,' in IEEE Symposium on VLSI Circuits (VLSI-Circuits), pp. 1-2, June. 2016. [43] A. M. Abo, et al., “A 1.5-V 10-bit 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter,” IEEE Journal of Solid-State Circuits, pp. 599-606, May. 1999. [44] J. Sauerbrey, D. Schmitt-Landsiedel and R. Thewes, 'A 0.5-V 1-μW successive approximation ADC,' IEEE Journal of Solid-State Circuits, pp. 1261-1265, July. 2003. [45] Wang, J. Ren, W. Yin, T. Chen and J. Xu, 'A High-Speed High-Resolution Low-Distortion CMOS Bootstrapped Switch,' 2007 IEEE International Symposium on Circuits and Systems, New Orleans, LA, USA, 2007 [46] H. Huang, et al., “A 1.2-GS/s 8-bit Two-Step SAR ADC in 65-nm CMOS with Passive Residue Transfer,” in IEEE Asian Solid-State Circuits Conf. Dig. Tech. Papers, pp. 289-292, Nov. 2015. [47] L. Kull, et al., “A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC with Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS,” IEEE Journal of Solid-State Circuits, pp. 3049-3058, Dec. 2013. [48] Y. Chung, M. Wu, and H. Li, 'A 12-bit 8.47-fJ/Conversion-Step Capacitor-Swapping SAR ADC in 110-nm CMOS,' IEEE Transactions on Circuits and Systems I: Regular Papers, pp. 10-18, Jan. 2015. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/84841 | - |
dc.description.abstract | Software-defined radar systems需要十億赫茲高取樣頻率的ADC 作為前端。連續寄進式(SAR) ADC在現代CMOS製程中具有很好的電能效率,因此適用於雷達系統的前端。 本作品文提出了一個在有時間偏移校正之十二位元每秒十億次取樣的時間交錯式連續漸進式類比至數位轉換器,實現於 TSMC 28nm CMOS,由一個 6-bit Coarse ADC 組成,並輔助四個 12-bit Fine ADC 實現高速、高解析度和低功耗。此外,時序偏移校準消除了通道之間的偏移效應。用於時序偏移校正,它與Subranging SAR ADC架構相結合,無需額外的參考通道。 本論文所提出的架構有兩個主要問題。第一個是穩壓非線性,第二個是Subranging SAR內部的頻寬不匹配。根據以前的量測經驗,穩壓非線性被低估,並限制了取樣頻率。Subranging SAR內部的頻寬不匹配會導致取樣誤差並限制輸入頻率。 電容製程不匹配和C-DAC穩壓非線性之間需要取捨。電容製程不匹配很難在模擬中驗證。儘管在R+C+CC模擬中可以觀察到C-DAC穩壓非線性;但是從之前的測量經驗來看我們低估了此效應。 本作品旨在通過兩種類型的 C-DAC 佈局來驗證電容製程不匹配和 C-DAC 穩壓非線性。第一個 TI SAR 使用具有高速穩壓的 C-DAC 佈局,具有較大的電容製程不匹配,第二個 TI SAR 使用具有穩壓非線性 C-DAC 佈局,並有較少的電容製程不匹配。 First TI SAR ADC的單通道測量結果在Fs=850MS/s與Fin=500kHz輸入頻率信號下,SNDR達到了51.54db,四通道測量結果達到了41. 31db。Secoond TI SAR ADC具有較好的電容匹配,但穩壓非線性較差。Secoond TI SAR ADC 的單通道量測結果在Fs=350MS/s與Fin=50kHz下,SNDR達到了 60.04 db而四通道測量達到了55.84db。 | zh_TW |
dc.description.abstract | Software-defined radar systems require the Gigahertz high sampling rate ADC as the front-end. Successive approximation-register (SAR) ADC is power efficient in the modern CMOS process, hence is suitable for the front-end of the radar system. This thesis proposed a 12-b 1-GS/s TI SAR ADC with Timing Skew calibration in 28nm CMOS, which consists of a 6-bit Coarse ADC to assist the four 12-bit Fine ADC in achieving high speed, high resolution, and low power. Besides, a Timing Skew calibration eliminates the skew effect between the channels. The Zero-Crossing algorithm is used in Timing Skew calibration, and it is combined with the Subranging architecture to eliminate the need for an additional reference channel. There is a trade-off between the capacitor process mismatch and C-DAC settling nonlinearity. Capacitor process mismatch is hard to verify in simulation. C-DAC settling nonlinearity can be observed in R+C+CC simulation; however, it is under-estimated. There are two significant problems with the proposed architecture. The first is the settling nonlinearity, and the second is the Subranging bandwidth mismatch. Settling nonlinearity is underestimated from the previous measurement experience, which limits the sampling rate. The Subranging bandwidth mismatch causes the sampling error and limits the input frequency. The proposed work aims at verified the capacitor process mismatch and C-DAC settling nonlinearity by two types of C-DAC layout. The First TI SAR uses the C-DAC layout with good settling linearity with large capacitor process mismatch, and the Second TI SAR uses the C-DAC layout with poor settling linearity with less capacitor process mismatch. The single-channel measurement result of the First TI SAR ADC achieves SNDR 51.54db at the conversion of 850MS/s with a 500kHz input signal, and the four-channel measurement result achieves SNDR 41.31db. The Second TI SAR ADC has better capacitor matching with the poor settling nonlinearity. At the conversion of 350MS/s with a 50kHz input signal, the single-channel measurement result of the Second TI SAR ADC achieves an SNDR of 60.04 db, and the four-channel measurement result of TI SAR ADC achieves an SNDR of 55.84db. | en |
dc.description.provenance | Made available in DSpace on 2023-03-19T22:28:29Z (GMT). No. of bitstreams: 1 U0001-2109202215545600.pdf: 6224551 bytes, checksum: c842441d44f17f41b224daeae89c98a6 (MD5) Previous issue date: 2022 | en |
dc.description.tableofcontents | 致謝 I 摘要 II Abstract IV Contents VI List of Figures IX Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 3 Chapter 2 Fundamentals of Analog-to-Digital Converter 4 2.1 Introduction 4 2.2ADC Architectures 4 2.2.1 Successive-Approximation-Register 4 2.3.2 Flash 5 2.2.3 Two-Step 7 2.2.4 Subranging 8 2.2.5 Time-Interleaved 8 2.2.5.1 Mismatch in Time-Interleaved ADC 9 2.2.5.1.1 Offset Mismatch 10 2.2.5.1.2 Gain Mismatch 13 2.2.5.1.3 Timing Skew Mismatch 16 2.2.5.1.4 TI Bandwidth Mismatch 20 2.2.5.2 Timing Skew Detection Method 22 2.2.5.2.1 Zero-Crossing Algorithm 22 2.2.5.2.2 Correlation-based 26 2.2.5.2.3 Variance-based algorithm 30 2.2.5.2.4 LMS Algorithm 31 2.3 Performance Metrics 32 2.3.1 Offset and Gain Error 32 2.3.2. Differential and Integral Nonlinearity (DNL and INL) 33 2.3.3 Signal-to-Noise Ratio (SNR) 34 2.3.4 Total Harmonic Distortion (THD) 34 2.3.5 Spurious-Free Dynamic Range (SFDR) 34 2.3.6 Signal to Noise and Distortion Ratio (SNDR) 35 2.3.7 Effective Number of Bits (ENOB) 35 2.3.8 Figure of Merit (FoM) 35 Chapter 3 Proposed 12-bit 1GS/s TI-SAR ADC 37 3.1Proposed Architecture 37 3.1.1 Coarse ADC 38 3.1.2 Fine ADC 41 3.1.3 Settling-Time Relief Technique 44 3.1.4 Error Correction Technique 45 3.1.5 Detect–and–Skip Algorithm 48 3.2 Fine C-DAC 50 3.2.1 Capacitor Process Mismatch 51 3.2.2 Subranging Bandwidth Mismatch with C-DAC Resistance 52 3.2.3 Fine C-DAC Settling Nonlinearity 53 3.2.3.1 Bottom Plate Switch time constant 54 3.2.3.2 Fine C-DAC Settling Nonlinearity Issue 60 3.2.3.3 Unit Capacitor Design in Fine C-DAC 63 3.2.3.4 Capacitor Array Design in Fine C-DAC 65 3.3 Zero-Crossing Calibration in Subranging Architecture 73 3.3.1 Proposed Timing Skew Calibration Scheme 74 3.3.2 Skew Calibration Parameter Consideration 77 3.3.2.1 Skew Requirements for 12-bit 1GS/s ADCs 77 3.3.2.2 Calibration Sampling Point 78 3.3.2.3 Step Size 79 3.3.3Timing Fluctuation 80 3.3.3.1 Timing Fluctuation Effect 81 3.3.3.2 Timing Fluctuation Caused by Referencing Scheme 83 3.3.3 Summary 85 Chapter 4 Circuit Implementation 86 4.1 Introduction 86 4.2 Bootstrapped Circuit 86 4.2.1 Linearity of Bootstrapped Circuit in High Sampling Rate 88 4.2.2 Input Bandwidth 89 4.2.3 Simulation Result 90 4.3 Clock Generator 91 4.4 On-Chip Adjustment Circuit 94 4.5 Comparator Circuit 99 4.5.1 Speed 100 4.5.2 Noise 102 4.5.3 Offset 104 4.5.4 Simulation Result 105 4.6 SAR Digital Logic 105 4.7 ADC Simulation Result 107 4.7.1 Post-Layout Simulation 107 4.7.2 Bond wire 113 Chapter 5 Measurement Setup and Result 118 5.1 Test Setup 118 5.1.1 Layout 119 5.1.2 PCB Design 120 5.2 Measurement Result 125 5.2.1 Static Performance 125 5.2.2 Dynamic Performance 126 5.2.3 Discussion 129 5.2.3.1 C-DAC Settling Nonlinearity 130 5.2.3.2 TI Gain Mismatch 131 5.2.3.3 Subrainging Gain Mismatch 133 5.2.3.4 Reference Ripple 136 5.2.3.5 Input Distortion 137 5.2.3.6 Input Bandwidth Mismatch 138 5.2.4 Power Dissipation 138 5.2.5 Summary 139 Chapter 6 Conclusion and Future Work 141 6.1 Conclusion 141 6.2 Future Work 142 Bibliography 145 | |
dc.language.iso | zh-TW | |
dc.title | 一個有時間偏移校正之十二位元每秒十億次取樣的時間交錯式連續漸進式類比至數位轉換器 | zh_TW |
dc.title | A 12-b 1-GS/s TI SAR ADC with Timing Skew Calibration | en |
dc.type | Thesis | |
dc.date.schoolyear | 110-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 洪崇智(Chung-Chih Hung),鍾勇輝(Yung-Hui Chung),胡耀升(Yao-Sheng Hu) | |
dc.subject.keyword | 類比至數位轉換器,時間交錯式,連續漸進式,分段連續漸進式,零交越時脈偏移校正,電容製程不匹配,分段增益不匹配,時間交錯式增益不匹配,時間交錯式頻寬不匹配,電容穩壓非線性, | zh_TW |
dc.subject.keyword | analog-to-digital converter,time-interleaved,successive-approximation register,Subranging SAR, zero-crossing timing skew calibration,zero-crossing timing skew calibration,capacitor process mismatch,Subranging gain mismatch,TI gain mismatch,TI bandwidth mismatch,C-DAC settling nonlinearity, | en |
dc.relation.page | 153 | |
dc.identifier.doi | 10.6342/NTU202203740 | |
dc.rights.note | 同意授權(限校園內公開) | |
dc.date.accepted | 2022-09-29 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
dc.date.embargo-lift | 2022-10-20 | - |
顯示於系所單位: | 電子工程學研究所 |
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