增強型氮化鎵電晶體導通暫態分析與閘極電阻最佳化設計

Abstract

近年來，高切換頻率之功率轉換器被廣泛應用於各式各樣的電子消費性產品中。高切換頻率功率轉換器有許多優點，包括更高的功率密度、更快速的暫態響應。隨著此趨勢，寬能隙元件如氮化鎵元件逐漸崛起，對比起傳統矽元件，氮化鎵元件更適合應用在高切換頻率的功率轉換器。然而在高頻應用下，氮化鎵元件的閘極驅動存在挑戰，相較於其他元件，氮化鎵元件的閘極較為脆弱，會因為電路板上寄生元件產生的額外電壓導致閘極過壓進而導致元件崩潰，此時閘極電路上的電阻扮演著抑制高頻效應的角色，但是傳統上設計閘極電阻的方式並未完善而會產生過度設計的問題。本論文提出針對增強型氮化鎵元件的驅動電路上閘極電阻設計最佳化，藉由以結構建立的氮化鎵元件等效電路模型，並運用雙脈衝實驗分析氮化鎵元件的切換行為，使用數學建模，找出在不同切換條件下合理的閘極電阻設計區間，也運用電腦軟體分析實體電路上的寄生電感參數，藉由還原真實寄生參數增加數學模型的精準度，並且透過電路模擬軟體與實際量測驗證模型，計算在不同閘極電阻下的切換損耗，以此論文之方式可以更精確地設計驅動氮化鎵元件的閘極電阻，使得過壓現象能避免，並且透過實際驗證切換損耗在設計下優於傳統設計。

In recent years, high switching frequency power converters are widely used in consumers’ electronic applications. High switching frequency converters feature high power-density and fast transient response. With this trend, wide bandgap components such as GaN devices have risen, they are more suitable for high frequency applications comparing to traditional silicon devices. However, there are issues of GaN devices gate driving need to be solved. One main issue is the fragility of gate. The induced voltage by parasitic components on the PCBs will damage the devices in high frequency applications. The gate resistance acts as the role to suppress the parasitic effects, but the design of the gate resistance is not optimized. This thesis proposes the optimization of the gate resistance. By modelling the GaN devices by their physical structure, double pulse test experiment is taken for analyzing the switching transition. The mathematical model is done in this thesis to find out the reasonable region for the gate resistance design. The parasitic extraction by software tool is also taken for the accurate analysis. With the verification by circuit simulation tools and hardware implementation, the switching loss and resistance design region can be obtained and the performance is verified to be better by proposed method.