請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/84624完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 黃俊郎(Jiun-Lang Huang) | |
| dc.contributor.author | Hao Cheng | en |
| dc.contributor.author | 程浩 | zh_TW |
| dc.date.accessioned | 2023-03-19T22:18:03Z | - |
| dc.date.copyright | 2022-09-19 | |
| dc.date.issued | 2022 | |
| dc.date.submitted | 2022-09-19 | |
| dc.identifier.citation | [1] J. L. H. David A. Patterson, Computer Organization and Design RISC-V Edition: The Hardware Software Interface, p. 169. 2020. [2] N. Kranitis, A. Paschalis, D. Gizopoulos, and G. Xenoulis, “Software-based selftesting of embedded processors,” IEEE Transactions on Computers, vol. 54, no. 4, pp. 461–475, 2005. [3] K. Kambe, M. Inoue, and H. Fujiwara, “Efficient template generation for instructionbased self-test of processor cores,” in 13th Asian Test Symposium, pp. 152–157, 2004. [4] M. Nakazato, S. Ohtake, M. Inoue, and H. Fujiwara, “Design for testability of software-based self-test for processors,” in 2006 15th Asian Test Symposium, pp. 375–380, 2006. [5] P. Bernardi, S. De Luca, D. Piumatti, S. Regis, E. Sanchez, and A. Sansonetti, “On the in-field testing of spare modules in automotive microprocessors,” in 2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), pp. 1–6, 2017. [6] P. Georgiou, X. Kavousianos, R. Cantoro, and M. Sonza Reorda, “Fault-independent test-generation for software-based self-testing,” IEEE Transactions on Device and Materials Reliability, vol. 19, no. 2, pp. 341–349, 2019. [7] L. Chen, S. Ravi, A. Raghunathan, and S. Dey, “A scalable software-based self-test methodology for programmable processors,” in Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451), pp. 548–553, 2003. [8] K.-H. Chen, B.-Y. Yang, J.-R. Liang, H.-L. Chen, and J.-L. Huang, “Automatic test program generation for transition delay faults in pipelined processors,” in 2021 IEEE International Test Conference in Asia (ITC-Asia), pp. 1–6, 2021. [9] S. Guramurthy, S. Vasudevan, and J. Abraham, “Automated mapping of precomputed module-level test sequences to processor instructions,” in IEEE International Conference on Test, 2005., pp. 10 pp.–303, 2005. [10] Y. Zhang, K. Chakrabarty, Z. Peng, A. Rezine, H. Li, P. Eles, and J. Jiang, “Softwarebased self-testing using bounded model checking for out-of-order superscalar processors,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 3, pp. 714–727, 2020. [11] L. Lingappan and N. K. Jha, “Satisfiability-based automatic test program generation and design for testability for microprocessors,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 15, no. 5, pp. 518–530, 2007. [12] Y. Zhang, A. Rezine, P. Eles, and Z. Peng, “Automatic test program generation for out-of-order superscalar processors,” in 2012 IEEE 21st Asian Test Symposium, pp. 338–343, 2012. [13] M. Psarakis, D. Gizopoulos, M. Hatzimihail, A. Paschalis, A. Raghunathan, and S. Ravi, “Systematic software-based self-test for pipelined processors,” in 2006 43rd ACM/IEEE Design Automation Conference, pp. 393–398, 2006. [14] Y. Zhang, H. Li, and X. Li, “Software-based self-testing of processors using expanded instructions,” in 2010 19th IEEE Asian Test Symposium, pp. 415–420, 2010 [15] A. Riefert, R. Cantoro, M. Sauer, M. Sonza Reorda, and B. Becker, “A flexible framework for the automatic generation of sbst programs,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 10, pp. 3055–3066, 2016. [16] M. K. Ganai and A. Gupta, “Accelerating high-level bounded model checking,” in 2006 IEEE/ACM International Conference on Computer Aided Design, pp. 794–801, 2006. [17] A. Waterman and K. Asanovi ´c, “The risc-v instruction set manual,” tech. rep., SiFive Inc., CS Division, EECS Department, University of California, Berkeley, andrew@sifive.com, krste@berkeley.edu, 2017. [18] C.-J. Lee, “Development of self-test program template with full pipeline coverage,” Master’s thesis, National Taiwan University, 2022. [19] F. Towhidi, A. Habibi Lashkari, and R. S. Hosseini, “Binary decision diagram (bdd),” in 2009 International Conference on Future Computer and Communication, pp. 496–499, 2009. [20] H.-L. Chen, “Case study: Test program generation of risc-v processor for softwarebased self-test,” Master’s thesis, National Taiwan University, 2021. [21] “Minisat.” http://minisat.se/. Accessed: 2022-08-03. [22] B.-Y. Yang, “Automatic pattern-to-program conversion methodology for softwarebased self-test,” Master’s thesis, National Taiwan University, 2020. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/84624 | - |
| dc.description.abstract | 處理器在產品生命週期內的可靠性需求隨著應用的發展而增加。在此使用情境下軟體自我測試(Software-Based Self-Test)被認為是一種解決辦法。然而過去大多數的研究在生成測試程式時都牽涉到大量的硬體設計知識，這使得自動化程度降低。在本論文中，我們提出了一種只使用到簡單設計知識的自動測試程式生成器。它的基本概念是用指令序列實現自動測試圖樣生產器(Automatic Test Pattern Generation)所生成的檢測狀態。我們的核心技術是將檢測狀態視為要被滿足的值並尋找能夠使之滿足的主要輸入，藉此推導出能實現檢測狀態的指令序列。為了刪減滿足性問題(satisfiability)的搜尋空間，我們的方法將測試樣板與滿足性解答器結合並提出了一種基於檢測狀態統計來決定滿足順序的方法，它能夠維持測試品質並加速測試程式生成。 此外，針對暫存器堆(Register file)這種常見的模組，我們也提出了一個可根據流水線結構調整的通用測試樣板。它能夠提升測試品質與測試效率。透過所提方法，我們在一個RISC-V處理器上達到90.4%的轉態延故障誤覆蓋率(transition delay fault coverage)。 | zh_TW |
| dc.description.abstract | For processor cores, reliability demand over the product life increase as applications evolve. Software-Based Self-Test (SBST) is considered a solution in this scenario. However, most of the prior SBST techniques involved a lot of hardware design knowledge. In this thesis, we propose an automatic test program generation using trivial design knowledge only. The basic idea is realizing the automatic test pattern generation (ATPG) generated detection state with an instruction sequence. Our key technique treats the detection state as the values-to-be-satisfied and satisfies them by specifying primary inputs (PIs) which are used to derive instruction sequence. To reduce the search space of solving satisfiability (SAT), we combine template and SAT solver and define the priority of values-to-be-satisfied. Based on the statistics of detection states, the definition of priority speeds up the test program generation. For the register file, we propose a generic test template that is adjustable according to the processor’s pipeline architecture. The template helps to improve the test quality and test efficiency. The proposed method is validated on a RISC-V processor and achieves 90.4% transition delay fault coverage. | en |
| dc.description.provenance | Made available in DSpace on 2023-03-19T22:18:03Z (GMT). No. of bitstreams: 1 U0001-1409202215084200.pdf: 3659909 bytes, checksum: 67efc213634de992f1509e7e6e51765e (MD5) Previous issue date: 2022 | en |
| dc.description.tableofcontents | Acknowledgements i 摘要 ii Abstract iii Chapter 1 Introduction 1 1.1 Software-Based Self-Test (SBST) 1 1.2 Related work 2 1.3 Motivation 5 1.4 Contribution 6 1.5 Organization of the Thesis 7 Chapter 2 Preliminaries 8 2.1 Previous work: single-template-based SBST 8 2.2 RISC-V instruction set architecture 11 2.3 Binary decision diagram (BDD) 13 Chapter 3 Proposed Method 16 3.1 Test program generation flow 16 3.2 SAT-based pattern-to-program conversion 17 3.2.1 Core technology of the proposed conversion 20 3.2.1.1 Longer detection sequence 20 3.2.1.2 Combination of template and SAT 22 3.2.1.3 Multiple solution SAT solver 23 3.2.1.4 Priority mechanism 23 3.2.2 Build circuit model 27 3.2.3 Evaluate PPO priority 27 3.2.4 Derive detection sequence 28 3.2.4.1 Comparison with sequential ATPG 31 3.2.4.2 Satisfy PPO with PI/PPI 31 3.2.4.3 PASCA SAT 33 3.2.4.4 PASCA* SAT 36 3.2.4.5 Legalize derived instruction 40 3.2.5 Test segment optimization 41 3.2.5.1 Branch and jump handling 41 3.2.5.2 Improvement of Store Back 41 3.3 Test generation for RF 43 3.3.1 TDF in D port of DFF 43 3.3.2 TDF in Q port of DFF 43 3.3.3 Register file template 45 3.3.4 Optimization for using RF template 46 Chapter 4 Experiment Result 48 4.1 Experiment Setup 48 4.2 Fault coverage 50 4.3 Test generation time 52 4.4 Test program size 53 4.5 ATPG assigned frequency of DFF 55 4.6 Conversion efficiency 57 4.7 Effect of cost definition 58 4.8 Effect of RF test generation 59 Chapter 5 Conclusion and Future Work 61 5.1 Conclusion 61 5.2 Future Work 62 References 63 | |
| dc.language.iso | en | |
| dc.title | 可滿足性基礎的自動測試程式生成 | zh_TW |
| dc.title | SAT-based Automatic Test Program Generation | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 110-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 李進福(Jin-Fu Li),呂學坤(Shyue-Kung Lu) | |
| dc.subject.keyword | 自動測試程式生成,布林可滿足性,軟體自我測試,測試樣板,可靠性, | zh_TW |
| dc.subject.keyword | automatic test program generation,satisfiability,software-based self-test,test template,reliability, | en |
| dc.relation.page | 65 | |
| dc.identifier.doi | 10.6342/NTU202203395 | |
| dc.rights.note | 同意授權(限校園內公開) | |
| dc.date.accepted | 2022-09-19 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| dc.date.embargo-lift | 2022-09-19 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
文件中的檔案：
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| U0001-1409202215084200.pdf 授權僅限NTU校內IP使用（校園外請利用VPN校外連線服務） | 3.57 MB | Adobe PDF | 檢視/開啟 |
系統中的文件，除了特別指名其著作權條款之外，均受到著作權保護，並且保留所有的權利。