請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/84395完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳中平(Chung-Ping Chen) | |
| dc.contributor.author | Wei-Ching Chang | en |
| dc.contributor.author | 張唯靖 | zh_TW |
| dc.date.accessioned | 2023-03-19T22:10:17Z | - |
| dc.date.copyright | 2022-03-07 | |
| dc.date.issued | 2022 | |
| dc.date.submitted | 2022-03-04 | |
| dc.identifier.citation | [1]“A 6.7MHz-to-1.24GHz 0.0318mm2 Fast-Locking All-Digital DLL in 90nm CMOS.'Min-Han Hsieh, IEEE ISSCC 2016. [2]“Relation Between Delay Line Phase Noise and Oscillator Phase Noise.'Behzad Razavi, JSSC 2014. [3]“An All-Digital Clock Generator Using a Fractionally Injection-Locked Oscilla- tor in 65nm CMOS.'P. Park, ISSCC 2012. [4]“A 0.026mm2 5.3mW 32-to-2000MHz Digital Fractional-N Phase Locked-Loop Using a Phase-Interpolating Phase-to-Digital Converter.'T.-K. Jang, ISSCC 2013. [5]”A 0.048mm2 3mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique” Wei Deng, ISSCC Digital Tech. papers, 2015. [6]“A Fractional-N, All-digital Injection-Locked PLL with Wide Tuning Range Digitally Controlled Ring Oscillator and Bang-Bang Phase Detection for Temperature Tracking in 40nm CMOS” W. Grollitsch, ESSCIRC, 12-15 Sept. 2016. [7],“Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor” Visvesh S. Sathe, JSSC, vol.48, page 140-149, January 2013. [8]“A 1.7GHz MDLL-Based Fractional-N Frequency Synthesizer with 1.4ps RMS Integrated Jitter and 3mW Power Using a 1b TDC” G. Marucci, ISSCC, Feb. 2014. [9]“A Low-Reference Spur MDLL-Based Clock Multiplier and Derivation of Discrete-Time Noise Transfer Function for Phase Noise Analysis” G. Tak, ISSCC, Feb. 2018. [10]“Covering VHF frequency band with novel DLL-based frequency synthesizer” M. Gholami, International Conference on Communications and Signal Processing, Pages 297 – 299, 2011. [11]“New method to synthesize the frequency bands with DLL-based frequency synthesizer” M. Gholami, International Conference on Communications and Signal Processing, Pages: 300 – 304, 2011. [12]“A UHF-band RFID Transmitter with Spur Reduction Technique using a DLL-based Spread-Spectrum Clock Generator” S. Kim, IEEE RFIC Symposium, Pages: 393 – 396, 2014. [13]'Design of Analog CMOS Integrated Circuits' Behzad Razavi, McGraw-Hill, 2001. [14]'RF Microelectronics' Behzad Razavi, Second Edition, Upper Saddle River, NJ: Prentice-Hall, 2012. [15]'Design of Integrated Circuit for Optical Communications' Behzad Razavi, McGraw-Hill, 2002. [16]'Communication Integrated Circuits' Jri Lee, Jri Lee’s Website, 2018. [17] Phase-locked loop, Shen-Iuan Liu, 滄海書局, 2007. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/84395 | - |
| dc.description.abstract | 本晶片為採用重複使用延遲線的頻率合成器，此晶片採用 TSMC 90 奈米製 程，下線面積約為 1mm x 1mm，核心電路面積約為 0.18mm x 0.25mm。在電源供 應 1V 下，延遲鎖定迴路的輸出為 800MHz，參考突波為-30.2dBc，功耗為 12.2 mW。(功耗包含輸出級) | zh_TW |
| dc.description.abstract | This chip is a frequency synthesizer that uses a reusable delay line. This chip uses TSMC 90nm process. The total area is about 1mm x 1mm, and core area is 0.18mm x 0.25mm. When the power supply is 1V, the maximum output of the delay locked loop is 800 MHz, and the reference spur is -30.2 dBc, power consumption is 12.2 mW.(Power including output buffer) | en |
| dc.description.provenance | Made available in DSpace on 2023-03-19T22:10:17Z (GMT). No. of bitstreams: 1 U0001-0103202214355100.pdf: 10400908 bytes, checksum: c6daf2d76088f85de6e8eaf308701593 (MD5) Previous issue date: 2022 | en |
| dc.description.tableofcontents | Contents Verification Letter from the Oral Examination Committee i Acknowledgements iii 摘要 v Abstract vii Contents ix List of Figures xiii List of Tables xvii Chapter1 Introduction 1 1.1 Related research and development status 1 1.2 Research motivation 2 Chapter2 Background 5 2.1 The basic concept of phase locked loop 5 2.2 Building blocks for phase locked loop 6 2.2.1 Phase/Frequency Detector and Charge Pump 6 2.2.2 Loop Filter 9 2.2.3 Voltage-Controlled Oscillator 10 2.2.4 Frequency Divider 12 2.3 Linear Model of Phase Locked Loop 13 2.3.1 Linear Model of Phase/Frequency Detector and Charge Pump 13 2.3.2 Linear Model of Loop Filter 14 2.3.3 Linear Model of Voltage-Controlled Oscillator 15 2.3.4 Linear Model of Frequency Divider 16 2.3.5 Stability Analysis of Phase-Locked Loop 17 2.4 General Design Procedures of Phase-Locked Loop 21 2.5 The Concept of Multiplying Delay-Locked Loop 22 2.5.1 Delay-Locked Loop 22 2.5.2 DLL-Based Frequency Synthesizer 22 Chapter3 An Area-Efficient Frequency Synthesizer Based on a Multiplying Delay-Locked Loop with a Reusable Delay Line 25 3.1 Introduction 25 3.2 System Structure 26 3.3 Design goals and Implement methods 28 3.3.1 Clock Separator 28 3.3.2 Phase Selector and Controller 29 3.3.3 Delay Line 33 3.3.4 Phase Detector 36 3.3.5 Digital Loop Filter 38 3.3.6 Edge Combiner 42 3.4Design Flow 42 3.5 Simulation Result 44 3.5.1 Function of Dual Ring 44 3.5.2 Function of Digital Loop Filter 44 3.5.3 Delay Range and Variation of DelayLine 45 3.5.4 Edge Combiner 48 3.5.5 Parasitic Issue 48 3.5.6 Locking Time 49 3.5.7 LockingBehavior, EyeDiagram 49 Chapter4 Experimental Results 53 4.1 Layout Floorplan 53 4.2 Measurement Environment 54 4.3 Measurement Results 56 Chapter5 Conclusion and Future Work 59 5.1 Conclusion 59 5.2 FutureWork 60 Chapter6 Reference 61 List of figures 2.1 The block diagram of conventional PLL 5 2.2 Phase detector 7 2.3 Typical PFD and CP 7 2.4 Timing diagram of the PFD 8 2.5 Transfer curve of the PFD/CP 9 2.6 The first order loop filter 9 2.7 (a) Second order (b) Third order loop filter 10 2.8 The block diagram of VCO and its transfer curve 10 2.9 Output spectrum with a small and periodical signal on Vctrl 12 2.10 Voltage-controlled current-starved ring oscillator 12 2.11 Divide-by-3/4 divider 13 2.12 Schematics of divide-by-3/4 divider 13 2.13 (a) First order, (b) Second order, (c) Third order loop filter 14 2.14 Divide-by-8 divider and its timing diagram 16 2.15 The linear model of PLL 17 2.16 Bode plot of the PLL with optimized phase margin 20 2.17 The typical Delay Locked Loop (DLL) 22 2.18 Traditional frequency synthesizer based on delay locked loop 23 3.1 System architecture diagram 27 3.2 Architecture flow chart 27 3.3 Clock Separator architecture diagram timing diagram 28 3.4 Phase Selector and Delay Line architecture diagram 29 3.5 Phase Selector timing diagram 30 3.6 Phase Selector architecture diagram 31 3.7 Implementation method of Phase Selector 32 3.8 Controller architecture diagram and implementation method 32 3.9 Architecture diagram of Delay Line and unit Delay Cell 34 3.10 Architecture diagram of how to controlling Select Signal 34 3.11 Timing diagram of circuit operation 36 3.12 Circuit diagram and characteristic curve of BBPD 37 3.13 Waveform of BBPD 38 3.14 Operation of Digital Loop Filter 39 3.15 Architecture diagram of Digital Loop Filter 40 3.16 3-bit DAC and Thermometer Decoder and architecture diagram 41 3.17 Simulation results of B1<0:2> in Digital Loop Filter 41 3.18 Simulation results of B2<0:2> in Digital Loop Filter 41 3.19 Simulation results of B3<0:5> in Digital Loop Filter 42 3.20 Architecture diagram of Edge Combiner 43 3.21 Design Flow 43 3.22 Simulation results when Delay Line starts working 44 3.23 Simulation results when the Delay Line ends working 45 3.24 Simulation results of the Digital Loop Filter 46 3.25 In the case of 0 degrees, 27 degrees, and 85 degrees, when B2<0:2>=3’b0 and B3<0:5>=6’b0, the Delay time of a Ring by adjusting B1<0:2> (Post-sim) 46 3.26 In the case of different corners (TT, SS, FF, SF, FS), when B2<0:2>=3’b0 and B3<0:5>=6’b0, the Delay time of a Ring by adjusting B1<0:2> (Post-sim) 47 3.27 In the case of 0 degrees, 27 degrees, and 85 degrees, when B1<0:2>=3’b0 and B2<0:3>=3’b0, the Delay time of a Ring by adjusting B3<0:5> (Post-sim) 47 3.28 In the case of different corners (TT, SS, FF, SF, FS), when B1<0:2>=3’b0 and B2<0:2>=3’b0, the Delay time of a Ring by adjusting B3<0:5> (Post-sim) 47 3.29 Simulation results of Edge Combiner and its output 48 3.30 Add the predicted measurement environment to the simulation 49 3.31 Locking Behavior 50 3.32 Eye Diagram 50 3.33 Locking Behavior 51 3.34 Eye Diagram 51 4.1 The layout diagram of the chip 53 4.2 The microphotograph of the chip and the core layout diagram 54 4.3 The photograph of the PCB 55 4.4 The measurement environment 55 4.5 Measured output spectrum(800MHz) 56 4.6 Measured output spectrum(600MHz) 57 List of Tables 2.1 Relationship between γ and PM. 20 4.1 Measured phase noise of signal generator 56 4.2 Comparison Table 57 | |
| dc.language.iso | zh-TW | |
| dc.subject | 環形電壓控制延遲線 | zh_TW |
| dc.subject | 頻率合成器 | zh_TW |
| dc.subject | 延遲鎖定迴路 | zh_TW |
| dc.subject | frequency synthesizer | en |
| dc.subject | delay-locked loop | en |
| dc.subject | ring-type voltage control delay line | en |
| dc.title | 一個利用重複使用的延遲線達到省面積的基於倍數式延遲鎖定迴路的頻率合成器 | zh_TW |
| dc.title | An Area-Efficient Frequency Synthesizer Based on a Multiplying Delay-Locked Loop with a Reusable Delay Line. | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 110-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 林宗賢(Tsung-Hsien Lin),曹恆偉(Hen-Wai Tsao) | |
| dc.subject.keyword | 頻率合成器,延遲鎖定迴路,環形電壓控制延遲線, | zh_TW |
| dc.subject.keyword | frequency synthesizer,delay-locked loop,ring-type voltage control delay line, | en |
| dc.relation.page | 63 | |
| dc.identifier.doi | 10.6342/NTU202200610 | |
| dc.rights.note | 同意授權(限校園內公開) | |
| dc.date.accepted | 2022-03-04 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| dc.date.embargo-lift | 2022-03-07 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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