一個應用於穿戴式裝置改善模式切換電壓漣波之三種模式非反向四開關升降壓直流轉換器

Abstract

近年來，應用於輸入為鋰電池輸出為百毫瓦消耗功率的穿戴式裝置晶片應用蓬勃發展，人們需要能升降壓的直流電壓轉換器解決方案。四開關非反向切換電感式的直流電壓轉換器因為其高輸出功率與大範圍功率操作區間比起全電容式或線性穩壓器的直流電壓轉換器更具有優勢而受到重視。 在穿戴式裝置的應用上，電源管理晶片講求低輸出漣波以及高效率，然而升降壓直流轉換器因為高電流峰對峰值往往伴隨低功率，使得同時具備兩者優點也成為切換電感式電壓轉換器設計的難題。以往的晶片透過三模式四開關非反向升降壓切換電感式轉換器架構。在輸入與輸出差異較大時以升壓與降壓模式減小輸出漣波和提高效率；而輸入與輸出電壓相近時，電路則是操作在升降壓模式，同時透過計算並壓縮升降壓模式區間提升整體效率，然而在模式之間因為工作佔週期比(Duty)不同，導致輸出電壓會在模式切換時透過補償電路來把工作佔週期比(Duty)往新模式的值變動，也就產生極大的模式轉換輸出電壓變化。 本論文透過提出的自動延遲斜波控制(Auto-Delay-Ramp)方法在三模式四開關非反向升降壓切換電感式轉換器架構，設計一個應用於輸入為鋰電池且輸出為百毫瓦消耗穿戴式裝置的低轉換模式漣波且高效率電源轉換器。 此晶片透過台積電0.18μm 1P6M High Voltage Mixed Signal CMOS製程實現，依據實驗結果，本晶片在輸出負載為一百毫安培同時輸出為三點三伏特模式切換時，瞬間輸出電壓變化約為小於0.848%，暫態反應時間約為小於21.48μs，負載電流範圍從20毫安培(mA)到350毫安培(mA)，最高效率在負載為100毫安培(mA)時為96.62%，提出的自動延遲斜波控制(Auto-Delay-Ramp)方法有效的減少模式切換的輸出電壓漣波。

Recently, people need the solution of DC-DC Converter that can save a lot of cost and size because the application of hundreds of mW wearable devices flourishes. People pay attention to Four-Switch Non-Inverting Buck-Boost DC-DC Converter(FSNIBBC) because it has more power capacity than the Switching-Capacitor Converter, and it can provide both higher and lower than one conversion ratio, which the Linear Regulator cannot. Power management chips focus on high efficiency and small output voltage ripples of wearable devices. However, the FSNIBBC usually has low conversion efficiency because of the high inductor peak-to-peak current. The proposed chip uses a Three-Mode FSNIBBC structure to increase conversion efficiency when the input voltage is much higher or lower than the output voltage. However, when the mode transitions from each mode, it would be a significant Duty gap to let the compensator settle to the new Duty level, which means vast output voltage ripples. This thesis uses the proposed Auto-Delay-Ramp on the Three-Mode FSNIBBC. By doing so, a low mode transition voltage ripples and high-efficiency power converter will be implemented for wearable applications. The proposed chip is fabricated in TSMC 0.18 μm 1P6M High Voltage Mixed-Signal CMOS process. It can provide a fixed output voltage of 3.3V at loading is 20 mA~ 350mA when the input voltage is 2.7V to 4.2V. The measurement results with Auto-Delay-Ramp will effectively reduce output voltage ripples when mode transition to less than 0.848% and settling time less than 21.48uSec, and the maximum efficiency is 96.62% at output current equal to 100mA.