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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 李泰成(Tai-Cheng Lee) | |
dc.contributor.author | Che-Wei Chang | en |
dc.contributor.author | 張哲維 | zh_TW |
dc.date.accessioned | 2023-03-19T21:07:09Z | - |
dc.date.copyright | 2022-09-26 | |
dc.date.issued | 2022 | |
dc.date.submitted | 2022-09-18 | |
dc.identifier.citation | [1] Y.-C. Chan, “Design and Analysis of a SAR-ISDM ADC with Gated-delay Oscillator Integrator,” Master’s thesis, National Taiwan University, Taipei, Taiwan, Jan. 2020. [2] S. Pavan, R. Schreier, and G. C. Temes, Understanding Delta-Sigma Data Converters. Wiley-IEEE Press, second ed., 2017. [3] J. Markus, J. Silva, and G. Temes, “Theory and Applications of Incremental ΔΣ Converters,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, pp. 678–690, Apr. 2004. [4] S.-E. Hsieh and C.-C. Hsieh, “A 0.4V 13b 270kS/S SAR-ISDM ADC with an Opamp-Less Time-Domain Integrator,” in IEEE ISSCC Dig. Tech. Papers, pp. 240–242, Feb. 2018. [5] S.-E. Hsieh and C.-C. Hsieh, “A 0.4-V 13-bit 270-kS/s SAR-ISDM ADC With Opamp-Less Time-Domain Integrator,” IEEE J. Solid-State Circuits, vol. 54, pp. 1648–1656, June 2019. [6] B. Razavi, Principles of Data Conversion System Design. Wiley-IEEE Press, 1994. [7] K. M. Tony Chan Carusone, David Johns, Analog Integrated Circuit Design. John Wiley & Sons, second ed., 2011. [8] C.-C. Liu, S.-J. Chang, G.-Y. Huang, and Y.-Z. Lin, “A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure,” IEEE J. Solid-State Circuits, vol. 45, pp. 731–740, Apr. 2010. [9] T. C. Caldwell and D. A. Johns, “Incremental Data Converters at Low Oversampling Ratios,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, pp. 1525–1537, July 2010. [10] Y.-L. Hsieh and T.-C. Lee, “A SAR-Assisted Continuous-Time Incremental ΣΔ ADC With First-Order Noise Coupling,” in IEEE Int. Conf. ASIC (ASICON), pp. 1–4, Oct. 2019. [11] K. Kim, Y. Kim, W. Yu, and S. Cho, “A 7b, 3.75ps Resolution Two-Step Time-to-Digital Converter in 65nm CMOS Using Pulse-Train Time Amplifier,” in Symp. VLSI Circuits Dig. Tech. Papers, pp. 192–193, June 2012. [12] Y.-H. Seo, J.-S. Kim, H.-J. Park, and J.-Y. Sim, “A 1.25 ps Resolution 8b Cyclic TDC in 0.13 μm CMOS,” IEEE J. Solid-State Circuits, vol. 47, pp. 736–743, Mar. 2012. [13] S.-K. Lee, Y.-H. Seo, H.-J. Park, and J.-Y. Sim, “A 1 GHz ADPLL With a 1.25 ps Minimum-Resolution Sub-Exponent TDC in 0.18μm CMOS,” IEEE J. Solid-State Circuits, vol. 45, pp. 2874–2881, Dec. 2010. [14] M. Z. Straayer and M. H. Perrott, “A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping,” IEEE J. Solid-State Circuits, vol. 44, pp. 1089–1098, Apr. 2009. [15] K. Lee, G. C. Temes, and F. Maloberti, “Noise-Coupled Multi-Cell Delta-Sigma ADCs,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 249–252, May 2007. [16] C.-C. Liu, S.-J. Chang, G.-Y. Huang, Y.-Z. Lin, and C.-M. Huang, “A 1V 11fJ/Conversion-Step 10bit 10MS/s Asynchronous SAR ADC in 0.18μm CMOS,” in Symp. VLSI Circuits Dig. Tech. Papers, pp. 241–242, June 2010. [17] B. P. Ginsburg and A. P. Chandrakasan, “500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC,” IEEE J. Solid-State Circuits, vol. 42, pp. 739–747, Apr. 2007. [18] A. Abo and P. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter,” IEEE J. Solid-State Circuits, vol. 34, pp. 599–606, May 1999. [19] C.-C. Liu, C.-H. Kuo, and Y.-Z. Lin, “A 10 bit 320 MS/s Low-Cost SAR ADC for IEEE 802.11ac Applications in 20 nm CMOS,” IEEE J. Solid-State Circuits, vol. 50, pp. 2645–2654, Nov. 2015. [20] J.-H. Tsai, H.-H. Wang, Y.-C. Yen, C.-M. Lai, Y.-J. Chen, P.-C. Huang, P.-H. Hsieh, H. Chen, and C.-C. Lee, “A 0.003 mm2 10 b 240 MS/s 0.7 mW SAR ADC in 28 nm CMOS With Digital Error Correction and Correlated-Reversed Switching,” IEEE J. Solid-State Circuits, vol. 50, pp. 1382–1398, June 2015. [21] Y.-Z. Lin, C.-H. Tsai, S.-C. Tsou, and C.-H. Lu, “A 8.2-mW 10-b 1.6-GS/s 4× TI SAR ADC with Fast Reference Charge Neutralization and Background Timing-Skew Calibration in 16-nm CMOS,” in Symp. VLSI Circuits Dig. Tech. Papers, pp. 1–2, June 2016. [22] H. S. Bindra, C. E. Lokin, D. Schinkel, A.-J. Annema, and B. Nauta, “A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise,” IEEE J. Solid-State Circuits, vol. 53, pp. 1902–1912, July 2018. [23] K. Ohhata, “A 2.3-mW, 1-GHz, 8-Bit Fully Time-Based Two-Step ADC Using a High-Linearity Dynamic VTC,” IEEE J. Solid-State Circuits, vol. 54, pp. 2038–2048, July 2019. [24] B. Razavi, Design of Analog CMOS Integrated Circuits. McGraw-Hill, second ed., 2016. [25] B. Razavi, Design of CMOS Phase-Locked Loops: From Circuit Level to Architecture Level. Cambridge University Press, 2020. [26] T. Miki, T. Morie, K. Matsukawa, Y. Bando, T. Okumoto, K. Obata, S. Sakiyama, and S. Dosho, “A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques,” IEEE J. Solid-State Circuits, vol. 50, pp. 1372–1381, June 2015. [27] B. Murmann, “ADC Performance Survey 1997-2022.” [Online]. Available: http://web.stanford.edu/~murmann/adcsurvey.html. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/83419 | - |
dc.description.abstract | 本論文提出一個單通道兩階混合式類比數位轉換器用於高功率效率的資料轉換,由循序漸進式類比數位轉換器為粗分轉換及時域增量式積分三角調變器為細分轉換所組成。以增量式積分三角調變器為細分轉換中,在採用門控延遲振盪器作為積分器達到一階雜訊移頻的基礎上,提出了一個一階時域雜訊耦合技術來實現有效的二階雜訊移頻。此外,也提出了一個雜訊耦合路徑。本論文對增量式積分三角調變器轉換的時間餘裕進行了分析以及對壓控振盪器和具有分離電壓時間轉換器的門控延遲振盪器進行了比較。 本晶片使用台積電四十奈米互補式金屬氧化物半導體製程實現,在取樣頻率為一千五百萬得到65.29分貝的訊號雜訊失真比、79.45分貝的無雜散動態範圍,並且功耗為2.72毫瓦。Schreier品質因素為159.7分貝,Walden品質因素為121 fJ/conversion-step。 | zh_TW |
dc.description.abstract | In this thesis, a single-channel two-step hybrid analog-to-digital converter (ADC), consisting of a successive approximation register (SAR) ADC and a time-domain incremental sigma-delta modulator (ISDM) for coarse and fine conversion, is proposed for power-efficient data conversion. On the basis of a gated-delay oscillator (GDO) as an integrator employed to achieve the first-order noise shaping in the fine ISDM conversion, a first-order time-domain noise coupling (TDNC) technique is proposed to realize the effective second-order noise shaping. In addition, the proposed noise-coupled path is also presented. The analysis of the time margin of the ISDM conversion and the comparison of a voltage-controlled oscillator (VCO) and the GDO with a separated voltage-to-time converter (VTC) are presented in this thesis. The proposed ADC fabricated in TSMC 40-nm CMOS technology achieves a signal-to-noise and distortion ratio (SNDR) of 65.29 dB and a spurious free dynamic range (SFDR) of 79.45 dB at a 15-MS/s sampling rate, and the power consumption is 2.72 mW. The Schreier figure of merit (FoM) is 159.7 dB, and the Walden FoM is 121 fJ/conversion-step. | en |
dc.description.provenance | Made available in DSpace on 2023-03-19T21:07:09Z (GMT). No. of bitstreams: 1 U0001-1709202212550300.pdf: 18640591 bytes, checksum: 57fa91120c3e9cd35373d46ee624e4e7 (MD5) Previous issue date: 2022 | en |
dc.description.provenance | Item reinstated by admin ntu (admin@lib.ntu.edu.tw) on 2023-10-25T07:28:01Z Item was in collections: 電子工程學研究所 (ID: 66b81ab7-9b22-47a0-91dd-d96c5d1e90e1) No. of bitstreams: 1 U0001-1709202212550300.pdf: 18640591 bytes, checksum: 57fa91120c3e9cd35373d46ee624e4e7 (MD5) | en |
dc.description.tableofcontents | 誌謝 iii 摘要 iv Abstract v 1 Introduction 1 1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Thesis Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 Fundamental 3 2.1 Introduction of Analog-to-Digital Converters . . . . . . . . . . . . . . . 3 2.2 ADC Performance Metrics . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.3 Architecture of Two-Step ADCs . . . . . . . . . . . . . . . . . . . . . . 10 2.4 Successive Approximation Register ADCs . . . . . . . . . . . . . . . . . 11 2.5 Incremental Sigma-Delta ADCs . . . . . . . . . . . . . . . . . . . . . . 13 2.5.1 Decimation Filter . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.5.2 Input-Referred Noise of Incremental Sigma-Delta ADCs . . . . . 18 3 Proposed Architecture and Circuit Implementation 21 3.1 Basic Architecture of the SAR-ISDM ADC . . . . . . . . . . . . . . . . 21 3.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1.2 Time-Domain ISDM Operation . . . . . . . . . . . . . . . . . . 23 3.1.3 Modification of the Basic Architecture . . . . . . . . . . . . . . . 26 3.2 Proposed Architecture of the SAR-ISDM ADC with First-Order Time-Domain Noise Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.2.1 Proposed First-Order TDNC Technique . . . . . . . . . . . . . . 27 3.2.2 Implementation of the Time-Domain ISDM with the Proposed TDNC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.2.3 Behavioral Simulation Results . . . . . . . . . . . . . . . . . . . 35 3.3 Circuit Implementation of SAR ADC . . . . . . . . . . . . . . . . . . . 37 3.3.1 Capacitor Switching Procedure . . . . . . . . . . . . . . . . . . . 37 3.3.2 Bootstrapped Switch . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3.3 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.3.4 Capacitive-DAC . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.3.5 SAR Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.3.6 Dynamic Amplifier Control Logic . . . . . . . . . . . . . . . . . 46 3.4 Circuit Implementation of ISDM . . . . . . . . . . . . . . . . . . . . . . 47 3.4.1 Voltage-to-Time Converter . . . . . . . . . . . . . . . . . . . . . 48 3.4.2 Gated-Delay Oscillator . . . . . . . . . . . . . . . . . . . . . . . 53 3.4.3 Noise Coupling Circuits . . . . . . . . . . . . . . . . . . . . . . 53 3.4.4 Time Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.4.5 Digital Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.5 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.6 Output Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.7 Decimation Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.8 Layout Floor Plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.9 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.9.1 Pre-Layout Simulation Results . . . . . . . . . . . . . . . . . . . 63 3.9.2 Post-Layout Simulation Results . . . . . . . . . . . . . . . . . . 68 4 Analysis 72 4.1 Considerations of the Unit Capacitance of C-DAC . . . . . . . . . . . . . 72 4.2 VTC Nonlinearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.3 Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.3.1 SAR ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.3.2 ISDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.4 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.4.1 SAR ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.4.2 ISDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 4.4.3 Power Supply Noise of the Delay Line . . . . . . . . . . . . . . . 84 4.5 Biasing of the Dynamic Amplifier . . . . . . . . . . . . . . . . . . . . . 86 4.6 Time Margin of the ISDM Conversion . . . . . . . . . . . . . . . . . . . 88 4.7 Comparison of a VCO and the GDO with a Separated VTC . . . . . . . . 92 5 Experimental Results 96 5.1 Chip Micrograph and Printed Circuit Board . . . . . . . . . . . . . . . . 96 5.2 Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.3 Analog Front-End Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 101 5.4 Measured Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 5.4.1 The chip of the SAR-ISDM ADC . . . . . . . . . . . . . . . . . 102 5.4.2 The chip of the SAR-ISDM ADC with the proposed TDNC . . . 106 5.4.3 Performance Summary . . . . . . . . . . . . . . . . . . . . . . . 111 6 Conclusion 113 6.1 Comparison Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 6.2 Figure of Merit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Bibliography 116 | |
dc.language.iso | en | |
dc.title | 使用時域雜訊耦合的循序漸進-增量式積分三角類比數位轉換器之設計與分析 | zh_TW |
dc.title | Design and Analysis of a SAR-ISDM ADC with Time-Domain Noise Coupling | en |
dc.type | Thesis | |
dc.date.schoolyear | 110-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 劉深淵(Shen-Iuan Liu),林宗賢(Tsung-Hsien Lin) | |
dc.subject.keyword | 類比數位轉換器,循序漸進式類比數位轉換器,增量式積分三角調變器,高解析度,雜訊耦合,時間數位轉換器, | zh_TW |
dc.subject.keyword | Analog-to-digital converter (ADC),successive approximation register (SAR) ADC,incremental sigma-delta modulator (ISDM),high resolution,noise coupling,time-to-digital converter (TDC), | en |
dc.relation.page | 119 | |
dc.identifier.doi | 10.6342/NTU202203505 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2022-09-19 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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